公开(公告)号：KR1020040100303A

公开(公告)日：2004-12-02

申请号：KR1020030032599

申请日：2003-05-22

Applicant: 삼성전자주식회사

Inventor： 이상훈 ,  하상록 ,  서범석

IPC: H01L21/027

Abstract: PURPOSE: A bit of exposure equipment and an exposure method using the same are provided to perform simultaneously an exposure and an alignment on a shot of a wafer without a regular correction term by forming a plurality of first align marks on a reticle and a plurality of second align marks on the shot corresponding to the first align marks. CONSTITUTION: A bit of exposure equipment includes a wafer stage, a reticle, a light source, and a lens unit. The wafer stage(150) loads a wafer(140). The reticle(130) is installed over the wafer. The reticle includes a predetermined pattern(131). The light source(110) irradiates a ray of light. The lens unit(120) transmits the light to a shot(141) of the wafer via the reticle. A plurality of first align marks(132) are formed on the predetermined pattern of the reticle. A plurality of second align marks(142) are formed on the shot of the wafer corresponding to the first align marks, respectively.

Abstract translation: 目的：提供一些曝光设备和使用其的曝光方法，以通过在掩模版上形成多个第一对准标记并在多个 在与第一对准标记相对应的镜头上的第二对准标记。 构成：一些曝光设备包括晶片台，光罩，光源和透镜单元。 晶片台（150）装载晶片（140）。 掩模版（130）安装在晶片上。 掩模版包括预定图案（131）。 光源（110）照射光线。 透镜单元（120）经由掩模版将光透射到晶片的镜头（141）。 在掩模版的预定图案上形成多个第一对准标记（132）。 分别在对应于第一对准标记的晶片的镜头上形成多个第二对准标记（142）。

公开(公告)号：KR1020040099577A

公开(公告)日：2004-12-02

申请号：KR1020030031603

申请日：2003-05-19

Applicant: 삼성전자주식회사

Inventor： 김현룡 ,  하상록 ,  정주혁

IPC: H01L21/68

Abstract: PURPOSE: A transfer apparatus of semiconductor manufacturing equipment and a method of controlling the same are provided to improve the stability of a transferring process by using a photo-sensor and a light receiving part. CONSTITUTION: A transfer apparatus(200) includes a connection part, a transfer part, a driving part, a photo-diode, a light receiving part, and a controller. The connection part(260) is connected to a bit of semiconductor manufacturing equipment(290). The transfer part is used for transferring a wafer through the connection part into the equipment. The driving part(240) is connected to the transfer part. At this time, the driving part faces the connection part. The photo-sensor(270) is fixed on the connection part. The light receiving part is fixed on the driving part. The controller controls the motion of the transfer part corresponding to data provided from the photo-sensor and the light receiving part.

Abstract translation: 目的：提供一种半导体制造设备的传送装置及其控制方法，通过使用光传感器和受光部来提高传送处理的稳定性。 传送装置（200）包括连接部分，传送部分，驱动部分，光电二极管，光接收部分和控制器。 连接部分（260）连接到一点半导体制造设备（290）。 转印部分用于将晶片通过连接部分转移到设备中。 驱动部（240）与转印部连接。 此时，驱动部朝向连接部。 光传感器（270）固定在连接部上。 光接收部分固定在驱动部分上。 控制器控制对应于从光传感器和光接收部件提供的数据的传送部分的运动。

公开(公告)号：KR1020040081866A

公开(公告)日：2004-09-23

申请号：KR1020030016435

申请日：2003-03-17

Applicant: 삼성전자주식회사

Inventor： 손홍성 ,  하상록

IPC: H01L21/28

Abstract: PURPOSE: A method for forming a metal interconnection of a dual damascene structure is provided to improve process margin and reliability by effectively preventing destructive photoresist. CONSTITUTION: The first and second insulating layer are formed on a substrate(100) with a conductive pattern(90). The first insulating pattern(115a) having a via is formed to expose the conductive pattern by selectively etching the second and first insulating layer. At this time, nitrogen material is generated in the via. The nitrogen material is substituted by applying hydrogen. The second insulating pattern(125b) including a trench is formed by selectively etching the second insulating layer, thereby forming a dual damascene pattern. Then, a metal interconnection(160a) is formed in the dual damascene pattern.

Abstract translation: 目的：提供一种用于形成双镶嵌结构的金属互连的方法，以通过有效地防止破坏性光致抗蚀剂来改善工艺裕度和可靠性。 构成：第一绝缘层和第二绝缘层形成在具有导电图案（90）的基板（100）上。 具有通孔的第一绝缘图案（115a）形成为通过选择性地蚀刻第二绝缘层和第一绝缘层来露出导电图案。 此时，在通路中产生氮物质。 通过施加氢来代替氮材料。 通过选择性地蚀刻第二绝缘层形成包括沟槽的第二绝缘图案（125b），从而形成双镶嵌图案。 然后，在双镶嵌图案中形成金属互连（160a）。

公开(公告)号：KR1020040077311A

公开(公告)日：2004-09-04

申请号：KR1020030012823

申请日：2003-02-28

Applicant: 삼성전자주식회사

Inventor： 장호선 ,  하상록 ,  김일구 ,  박완재

IPC: H01L21/28

Abstract: PURPOSE: A dual damascene method for metal line is provided to prevent generation of undercut by performing a plasma dry-etch process for removing inorganic materials. CONSTITUTION: A diffusion barrier(14) is formed on a lower copper line(12). An inorganic interlayer dielectric(16), an etch-stop layer(18), and an insulating layer having a low dielectric constant are sequentially formed on the diffusion barrier. A via hole(34) is formed by performing an etch process. The via hole is buried by inorganic materials. A trench(30) is formed by performing the etch process. The lower copper line is exposed by removing the inorganic materials and the diffusion barrier from the via hole. In addition, the inorganic materials are removed by a dry-etch method using plasma of source gas including CxFy-gas, oxygen-contained gas, and inert gas.

Abstract translation: 目的：提供用于金属线的双镶嵌方法，以通过执行用于去除无机材料的等离子体干蚀刻工艺来防止产生底切。 构成：在下铜线（12）上形成扩散阻挡层（14）。 在扩散阻挡层上依次形成无机层间电介质（16），蚀刻停止层（18）和具有低介电常数的绝缘层。 通过执行蚀刻工艺形成通孔（34）。 通孔被无机材料掩埋。 通过执行蚀刻工艺形成沟槽（30）。 通过从通孔去除无机材料和扩散阻挡层来暴露下部铜线。 此外，通过使用包括C x F y，气体和惰性气体的源气体的等离子体的干蚀刻方法除去无机材料。

公开(公告)号：KR1020040074798A

公开(公告)日：2004-08-26

申请号：KR1020030010265

申请日：2003-02-19

Applicant: 삼성전자주식회사

Inventor： 박병률 ,  하상록 ,  정주혁 ,  손홍성

IPC: H01L21/28

Abstract: PURPOSE: A method for forming a metal line of a semiconductor device is provided to prevent a thinning phenomenon and a lifting phenomenon of the second photoresist pattern by using a dual damascene method. CONSTITUTION: The first interlayer dielectric pattern(120a) having the first trench is formed on a substrate(100). The second etch-stop layer is formed on the first interlayer dielectric pattern. The second etch-stop layer spacer is formed by etching back the second etch-stop layer. The second interlayer dielectric(140) is formed thereon. A mask pattern is formed on the second interlayer dielectric. The second trench is formed by etching the second interlayer dielectric. The mask pattern is removed therefrom. The first trench and the second trench are buried by metallic materials.

Abstract translation: 目的：提供一种用于形成半导体器件的金属线的方法，以通过使用双镶嵌方法来防止第二光致抗蚀剂图案的变薄现象和提升现象。 构成：具有第一沟槽的第一层间介质图案（120a）形成在基板（100）上。 第二蚀刻停止层形成在第一层间电介质图案上。 通过蚀刻第二蚀刻停止层来形成第二蚀刻停止层间隔物。 第二层间电介质（140）形成在其上。 在第二层间电介质上形成掩模图案。 通过蚀刻第二层间电介质形成第二沟槽。 从中去除掩模图案。 第一沟槽和第二沟槽被金属材料掩埋。

公开(公告)号：KR1020040074769A

公开(公告)日：2004-08-26

申请号：KR1020030010165

申请日：2003-02-18

Applicant: 삼성전자주식회사

Inventor： 박대근 ,  하상록 ,  정주혁 ,  오혁상 ,  이정우 ,  강기호

IPC: H01L27/04

Abstract: PURPOSE: A method for fabricating a MIM capacitor is provided to obtain a process margin in a cleaning process by forming a dielectric layer on a diffusion barrier of a metal line. CONSTITUTION: The first metal line(110a) and the second metal line(110b) are formed on a substrate(100). A diffusion barrier pattern for exposing the first metal line is formed on the substrate in order to prevent the damage of the second metal line. A dielectric layer is formed on the diffusion barrier pattern and the second metal line. A top electrode layer is formed on the dielectric layer. The first photoresist pattern is formed on the top electrode layer in order to define a capacitor region. A top electrode(140a) of a capacitor is formed by over-etching the exposed top electrode layer.

Abstract translation: 目的：提供一种用于制造MIM电容器的方法，以通过在金属线的扩散阻挡层上形成电介质层来获得清洁过程中的工艺余量。 构成：第一金属线（110a）和第二金属线（110b）形成在基板（100）上。 为了防止第二金属线的损伤，在基板上形成用于露出第一金属线的扩散阻挡图案。 在扩散阻挡图案和第二金属线上形成介电层。 在电介质层上形成顶部电极层。 为了限定电容器区域，在顶部电极层上形成第一光致抗蚀剂图案。 通过过度蚀刻暴露的顶部电极层来形成电容器的顶部电极（140a）。

公开(公告)号：KR1020040065601A

公开(公告)日：2004-07-23

申请号：KR1020030002639

申请日：2003-01-15

Applicant: 삼성전자주식회사

Inventor： 하상록 ,  박용우

IPC: H01L21/02

Abstract: PURPOSE: A gas supply line system is provided to prevent a mixing error of gases in lines for supplying plural gases by using plural controllers, a pneumatic controller, and an interruption controller. CONSTITUTION: A gas supply line system includes a plurality of lines, a plurality of controllers, and a pneumatic controller. The lines are used for transferring gases. The controllers(26,27) are installed on each line in order to control the flow of the gases. The pneumatic controller(25) is used for controlling a driving operation of the controller installed on the same line of the lines. The gas supply line system further includes an interruption controller(28) to control the flow of the line corresponding to the target gas. The interruption controller is connected to the pneumatic controller through an air flow line.

Abstract translation: 目的：提供一种气体供应系统，以防止通过使用多个控制器，气动控制器和中断控制器来供应多种气体的管线中的气体的混合误差。 构成：气体供应系统包括多条管线，多个控制器和气动控制器。 这些管线用于输送气体。 控制器（26,27）安装在每条线上，以便控制气体的流动。 气动控制器（25）用于控制安装在同一线路上的控制器的驾驶操作。 气体供应管线系统还包括用于控制与目标气体相对应的管线流动的中断控制器（28）。 中断控制器通过气流管线连接到气动控制器。

公开(公告)号：KR1020040065463A

公开(公告)日：2004-07-22

申请号：KR1020030002442

申请日：2003-01-14

Applicant: 삼성전자주식회사

Inventor： 하상록 ,  윤석규

IPC: H01L21/027

Abstract: PURPOSE: A wafer exposure apparatus is provided to control the size of beam corresponding to an area of a real exposure part of a wafer by adding a beam size control unit and a lens to a leveling part. CONSTITUTION: A wafer exposure apparatus includes a wafer, a leveling part(20) for controlling a horizontal degree of a wafer stage, and an exposure part for emitting beams to the wafer to form circuit patterns. The leveling part includes a beam source unit(21), a first beam diffraction grid(22), a beam reflection unit(25) for reflecting the beam of the first beam diffraction grid, a second beam diffraction grid(24), and a beam detection unit(23). The wafer exposure apparatus further includes a beam size control unit(28) installed on a beam path in order to control the size of the beam. The wafer exposure apparatus further includes a lens(29) for condensing the beam.

Abstract translation: 目的：提供晶片曝光装置，通过将光束尺寸控制单元和透镜添加到调平部分来控制对应于晶片的实际曝光部分的区域的光束的尺寸。 构成：晶片曝光装置包括晶片，用于控制晶片台的水平度的调平部（20）和用于向晶片发射光束以形成电路图案的曝光部。 平整部分包括光束源单元（21），第一光束衍射栅极（22），用于反射第一光束衍射栅格的光束的光束反射单元（25），第二光束衍射栅格（24）和 光束检测单元（23）。 晶片曝光装置还包括安装在光束路径上的光束尺寸控制单元（28），以便控制光束的尺寸。 晶片曝光装置还包括用于冷凝光束的透镜（29）。

公开(公告)号：KR1020040048599A

公开(公告)日：2004-06-10

申请号：KR1020020076517

申请日：2002-12-04

Applicant: 삼성전자주식회사

Inventor： 하상록 ,  송효준

IPC: H01L21/68

Abstract: PURPOSE: A semiconductor device manufacturing apparatus having a wafer centering correction system and a wafer centering method are provided to be capable of precisely aligning the first center of a rotating spin chuck and the second center of a wafer for improving productivity. CONSTITUTION: A semiconductor device manufacturing apparatus(101) is provided with a spin chuck(105) for supporting a wafer(102), a main controller, an arm for transferring the wafer to the spin chuck, and a wafer centering system. At this time, the wafer centering system includes a CCD(Charge Coupled Device) light emitting device(103) for irradiating light through each pixel of a two-dimensional array and a CCD light receiving device(104) opposite to the CCD light emitting device.

Abstract translation: 目的：提供一种具有晶片定心校正系统和晶片定心方法的半导体器件制造设备，以能够精确地对准旋转旋转卡盘的第一中心和晶片的第二中心，以提高生产率。 构成：半导体器件制造装置（101）具有用于支撑晶片（102）的旋转卡盘（105），主控制器，用于将晶片转移到旋转卡盘的臂和晶片定心系统。 此时，晶片定心系统包括用于将光照射到二维阵列的每个像素的CCD（电荷耦合器件）发光器件（103）和与CCD发光器件相对的CCD光接收器件（104） 。

公开(公告)号：KR1020040020142A

公开(公告)日：2004-03-09

申请号：KR1020020051597

申请日：2002-08-29

Applicant: 삼성전자주식회사

Inventor： 서범석 ,  하상록

IPC: H01L21/027

Abstract: PURPOSE: A semiconductor exposure system including a bake unit is provided to improve the efficiency and the productivity by installing the bake unit within the semiconductor exposure system to perform an exposure process and a post-bake process in offline. CONSTITUTION: A semiconductor exposure system(1) including a bake unit includes a bake unit(11). Apart from stem tracks(2,3) in a coating process and a developing process, the semiconductor exposure system(1) including the bake unit(11) is operated in offline. The bake unit of the semiconductor exposure system(1) is connected to a purge system. After a bake process is performed, the bake unit is purged by the purge system.

Abstract translation: 目的：提供包括烘烤单元的半导体曝光系统，以通过在半导体曝光系统内安装烘烤单元来提高效率和生产率，从而在离线状态下执行曝光处理和后烘烤处理。 构成：包括烘烤单元的半导体曝光系统（1）包括烘烤单元（11）。 除了涂覆工艺和显影过程中的干道（2,3）之外，包括烘烤单元（11）的半导体曝光系统（1）在离线状态下操作。 半导体曝光系统（1）的烘烤单元连接到清洗系统。 在进行烘烤处理之后，烘烤单元被吹扫系统清洗。