公开(公告)号：KR1019970006213B1

公开(公告)日：1997-04-24

申请号：KR1019920000210

申请日：1992-01-09

Applicant: 삼성전자주식회사

Inventor： 신홍재 ,  하정민 ,  김영욱

IPC: H01L21/31

Abstract: A method of forming a protective layer of a semiconductor device constructed in such a manner that plasma generates between a first electrode to which a high frequency is applied and a second electrode to which a low frequency is applied, to deposit a silicon nitride layer on an Al metal line formed on a semiconductor substrate by a predetermined thickness, the Al metal line being placed on the second electrode side, in which the ratio of the power applied to the second electrode to the power applied to the first electrode is above 70%. The frequency applied to the first electrode is 13.56MHz and frequency applied to the second electrode is 300KHz. The silicon nitride layer may be formed on a PSG layer which is formed on the Al line by a predetermined thickness.

Abstract translation: 一种形成半导体器件的保护层的方法，其以等离子体在施加高频的第一电极和施加低频的第二电极之间产生等离子体的方式构成，以将氮化硅层沉积在 Al金属线形成在半导体衬底上预定厚度，Al金属线放置在第二电极侧，其中施加到第二电极的功率与施加到第一电极的功率的比率高于70％。 施加到第一电极的频率为13.56MHz，施加到第二电极的频率为300KHz。 可以在形成在Al线上预定厚度的PSG层上形成氮化硅层。

公开(公告)号：KR100071494B1

公开(公告)日：1994-03-07

申请号：KR1019910004506

申请日：1991-03-21

Applicant: 삼성전자주식회사

Inventor： 김영욱 ,  하정민 ,  신홍재

IPC: H01L21/31

公开(公告)号：KR1019930011150A

公开(公告)日：1993-06-23

申请号：KR1019920020429

申请日：1992-11-02

Applicant: 삼성전자주식회사

Inventor： 하정민 ,  신홍재 ,  김영욱

IPC: H01L21/60

公开(公告)号：KR1019930008967A

公开(公告)日：1993-05-22

申请号：KR1019910019216

申请日：1991-10-30

Applicant: 삼성전자주식회사

Inventor： 권기원 ,  하정민 ,  강창석 ,  김영욱

IPC: H01L21/28

Abstract: 본 발명은 반도체장치의 제조방법에 관한 것으로, 제1전극, 유전체막, 및 제2전극을 구비하는 반도체장치의 제조방법에 있어서, 상기 유전체막에 산화탄탈륨을 사용할 경우, 상기 제1 및 제2 전극중의 어느 한 전극을 티타늄나이트라이드로 형성하는 것을 특징으로 한다. 따라서, 본 발명은, 상기 산화탄타륨으로 이루어지는 유전체막의 누설전류를 줄이고 파괴전압을 높이기 위해서, 종래 상기 산화탄탈륨을 증착한 후 2단계의 어닐링공정을 실시하던 것에 비해, 본 발명에서는 상기 산화탄탈륨과 직접 접촉하는 전극물질로 TiN을 도입함으로써 별도의 후속 열처리공정 없이도 상기 유전체막의 특성을 향상시킬 수 있다.

公开(公告)号：KR1019920018896A

公开(公告)日：1992-10-22

申请号：KR1019910004395

申请日：1991-03-20

Applicant: 삼성전자주식회사

Inventor： 하정민 ,  김영욱 ,  신홍재

IPC: H01L21/28 ,  H01L21/306

公开(公告)号：KR100518525B1

公开(公告)日：2005-10-04

申请号：KR1019990005387

申请日：1999-02-18

Applicant: 삼성전자주식회사

Inventor： 송원상 ,  하정민 ,  박정우 ,  이길광 ,  최태희

IPC: H01L29/70

Abstract: 기생커패시턴스를 줄일 수 있는 전계효과 트랜지스터 및 그 제조방법에 관해 개시한다. 이를 위해 본 발명은 선택적 에피택셜 성장(Selective Epitaxial Growth)에 의한 에피층(epi)을 갖는 전계효과 트랜지스터에서 게이트스페이서(gate spacer)가 형성되는 위치의 소정영역에 유전체막 대신에 에어캡(Air gap)이 형성된 3중 게이트스페이서(triple gate spacer) 구조의 전계효과 트랜지스터(FET) 및 제조방법을 제공한다.

公开(公告)号：KR100399352B1

公开(公告)日：2003-09-26

申请号：KR1020010018506

申请日：2001-04-07

Applicant: 삼성전자주식회사

Inventor： 유종렬 ,  박정우 ,  하정민 ,  최시영

IPC: H01L21/3063

CPC classification number: H01L29/66636 ,  H01L21/02052 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/02639 ,  H01L21/28525 ,  H01L21/28562 ,  H01L21/76879 ,  H01L29/7834

Abstract: A method of forming a semiconductor device using selective epitaxial growth (SEG) is provided. This method includes forming an insulating layer pattern having a window on a semiconductor substrate. The window exposes a predetermined region of the semiconductor substrate. The substrate having the window is cleaned, thereby removing any native oxide layer on the exposed substrate. The cleaned substrate is oxidized. Accordingly, a sacrificial oxide layer is formed thereon. The sacrificial oxide layer is removed. Thus, the exposed substrate has substantially no crystalline defects. A single crystalline semiconductor layer is then grown on the exposed substrate using SEG.

Abstract translation: 提供了使用选择性外延生长（SEG）形成半导体器件的方法。 该方法包括在半导体衬底上形成具有窗口的绝缘层图案。 该窗口暴露半导体衬底的预定区域。 清洁具有窗口的基板，从而去除暴露的基板上的任何自然氧化物层。 清洁的基材被氧化。 因此，在其上形成牺牲氧化物层。 牺牲氧化层被去除。 因此，暴露的衬底基本上没有晶体缺陷。 然后使用SEG在暴露的衬底上生长单晶半导体层。

公开(公告)号：KR1020010064034A

公开(公告)日：2001-07-09

申请号：KR1019990062149

申请日：1999-12-24

Applicant: 삼성전자주식회사

Inventor： 하정민 ,  송원상

IPC: H01L29/78

Abstract: PURPOSE: A manufacturing method of MOS(Metal Oxide Semiconductor) transistor with raised source/drain is provided to minimize parasitic capacitance between a gate and a source/drain with forming a shallow junction. CONSTITUTION: An isolation layer(4) is built on a semiconductor substrate(2) to define an active region and an inactive region. After doping an insulation layer, a doped polysilicon layer is vaporized. Patterning the insulation layer and the doped polysilicon layer, a gate isolation layer(6) and a gate electrode(8) are made. The side of gate electrode(8) is oxidized, and an oxide layer(10) is produced. A spacer is attached on the side of gate electrode(8) after doping and etched back a nitride layer. Using a SEG(Selectively Epitaxial Growth) method, an epitaxial layer(14a,14b) is made on the gate electrode(8) and the substrate(2). The nitride spacer is etched using a H3PO4 solution. An insulation layer(16) is constructed by vaporizing a plasma CVD oxide layer or nitride layer. Etching the insulation layer(16), a void is formed between the gate electrode(8) and the epitaxial layer(14b). Impurity ions are injected into the semiconductor substrate(2) and activated to build a source/drain(18).

Abstract translation: 目的：提供具有升高的源极/漏极的MOS（金属氧化物半导体）晶体管的制造方法，以使形成浅结的栅极和源极/漏极之间的寄生电容最小化。 构成：隔离层（4）构建在半导体衬底（2）上以限定有源区和非活性区。 在掺杂绝缘层之后，掺杂的多晶硅层被蒸发。 对绝缘层和掺杂多晶硅层进行构图，形成栅极隔离层（6）和栅电极（8）。 栅极（8）侧被氧化，生成氧化物层（10）。 在掺杂后将间隔物附着在栅电极（8）的侧面，并将氮化物层回蚀刻。 使用SEG（选择性外延生长）法，在栅极（8）和基板（2）上形成外延层（14a，14b）。 使用H 3 PO 4溶液蚀刻氮化物间隔物。 通过蒸发等离子体CVD氧化物层或氮化物层来构造绝缘层（16）。 对绝缘层（16）进行蚀刻，在栅电极（8）和外延层（14b）之间形成空隙。 将杂质离子注入到半导体衬底（2）中并被激活以构建源极/漏极（18）。

公开(公告)号：KR100272173B1

公开(公告)日：2000-11-15

申请号：KR1019980051263

申请日：1998-11-27

Applicant: 삼성전자주식회사

Inventor： 하정민 ,  김성호 ,  이해정 ,  박정우 ,  최지현

IPC: H01L21/26

Abstract: PURPOSE: A method for forming a shallow junction of a semiconductor device without a damage of ion implantation is provided to remove damage generated from an ion beam implantation process by irradiating an electron beam. CONSTITUTION: A dopant is implanted on a semiconductor substrate by performing an ion implantation process(10). In the ion implantation process, an implanting depth of the dopant is 500 to 2000 angstrom. An electron beam is irradiated on the semiconductor substrate after performing the ion implantation process(11). In the electron beam irradiation process, the energy of the electron beam is 1 to 50 kilo electron volt. The semiconductor substrate is activated by performing a thermal process(12).

Abstract translation: 目的：提供一种用于形成半导体器件的浅结而不损伤离子注入的方法，以通过照射电子束来消除由离子束注入工艺产生的损伤。 构成：通过进行离子注入工艺（10）将掺杂剂注入到半导体衬底上。 在离子注入工艺中，掺杂剂的注入深度为500至2000埃。 在进行离子注入工艺（11）之后，在半导体衬底上照射电子束。 在电子束照射过程中，电子束的能量为1〜50千伏电压。 通过执行热处理（12）来激活半导体衬底。

公开(公告)号：KR1020000004468A

公开(公告)日：2000-01-25

申请号：KR1019980025904

申请日：1998-06-30

Applicant: 삼성전자주식회사

Inventor： 하정민 ,  배대록 ,  김철성 ,  구자흠

IPC: H01L21/28

Abstract: PURPOSE: A method is provided to improve a thermal stability using a silicide film as a diffusion source. CONSTITUTION: The method comprises the steps of: forming a refractory silicide film having at least two metals and silicon on a semiconductor substrate(10) to form junction portions, implanting a dopant into the refractory silicide film, forming shallower junction portions beneath the refractory silicide film by heat-diffusing the implanted dopant beneath the silicide film. Thereby, it is possible to improve a thermal stability using a silicide film as the diffusion source capable of withstanding high temperature for forming the shallower junction portions.

Abstract translation: 目的：提供一种使用硅化物膜作为扩散源来提高热稳定性的方法。 构成：该方法包括以下步骤：在半导体衬底（10）上形成具有至少两种金属和硅的难熔硅化物膜以形成接合部分，将掺杂剂注入难熔硅化物膜中，在难熔硅化物下方形成较浅的接合部分 通过在硅化物膜下方对植入的掺杂剂进行热扩散来制造薄膜。 由此，可以使用硅化物膜作为能够承受用于形成较浅接合部的高温的扩散源来提高热稳定性。