公开(公告)号：KR1020010083349A

公开(公告)日：2001-09-01

申请号：KR1020000006547

申请日：2000-02-11

Applicant: 삼성전자주식회사

Inventor： 황홍규 ,  하상록

IPC: H01L21/8242

Abstract: PURPOSE: A method for manufacturing a broadly-planarized semiconductor device is provided to increase manufacturing yield, by preventing an upper electrode of a capacitor from being damaged by an excessive chemical mechanical polishing(CMP) process. CONSTITUTION: An interlayer dielectric and an etching stop layer(62) are sequentially formed on the entire surface of a high-stepped region having a capacitor and a low-stepped region adjacent to the high-stepped region. The upper end of the etching stop layer in the low-stepped region is not lower than at least the upper end of the capacitor. An insulation layer(64) is formed on the etching stop layer. A chemical mechanical etching process is performed until the etching stop layer on the low-stepped region is exposed. The remaining etching stop layer is eliminated.

Abstract translation: 目的：通过防止电容器的上部电极被过度的化学机械抛光（CMP）工艺损坏，来提供制造广泛平坦化的半导体器件的方法以提高制造成品率。 构成：在具有与高阶梯状区域相邻的电容器和低阶梯状区域的高阶梯形区域的整个表面上依次形成层间电介质和蚀刻停止层（62）。 低阶区域中的蚀刻停止层的上端至少不低于电容器的上端。 绝缘层（64）形成在蚀刻停止层上。 进行化学机械蚀刻处理，直到露出低台阶区域上的蚀刻停止层。 剩下的蚀刻停止层被消除。

公开(公告)号：KR1020040063352A

公开(公告)日：2004-07-14

申请号：KR1020030000739

申请日：2003-01-07

Applicant: 삼성전자주식회사

Inventor： 황유상 ,  황홍규

IPC: H01L21/28

Abstract: PURPOSE: A method for forming a semiconductor device is provided to reduce a short-circuit phenomenon between a gate electrode and a contact by prevent an etch stop layer covering a substrate from being eliminated while forming a deep contact hole in a core region and a peripheral region in a process for forming a bitline contact hole. CONSTITUTION: A transistor structure is formed in a substrate(1), including a gate whose upper part and sidewall are surrounded by a silicon nitride layer. A bitline contact pad in contact with a drain region in a cell region is formed. An interlayer dielectric is formed on the substrate having the bitline contact pad. The interlayer dielectric is patterned to form a bitline contact hole exposing the bitline contact pad in the cell region. A contact hole exposing an active region covered with an etch stop layer(17) formed of a silicon nitride layer is formed in the core region and the peripheral region. An exposure process is performed to form a photoresist pattern(39) that covers the cell region and exposes the core region and the peripheral region. The etch stop layer on the bottom of the contact hole in the core and peripheral regions is removed by using the photoresist pattern as an etch mask. By using the photoresist pattern as an ion implantation mask, Impurity ions are implanted into the bottom of the contact hole from which the etch stop layer is removed.

Abstract translation: 目的：提供一种用于形成半导体器件的方法，以通过防止覆盖衬底的蚀刻停止层在芯区域和外围区域形成深接触孔的同时消除栅电极和接触件之间的短路现象 形成位线接触孔的过程中的区域。 构成：晶体管结构形成在衬底（1）中，包括其上部和侧壁被氮化硅层包围的栅极。 形成与单元区域中的漏极区域接触的位线接触焊盘。 在具有位线接触焊盘的基板上形成层间电介质。 图案化层间电介质以形成暴露电池区域中的位线接触焊盘的位线接触孔。 在核心区域和周边区域中形成露出由氮化硅层形成的蚀刻停止层（17）的有源区域的接触孔。 进行曝光处理以形成覆盖单元区域并使芯区域和周边区域露出的光致抗蚀剂图案（39）。 通过使用光致抗蚀剂图案作为蚀刻掩模，去除芯和外围区域中的接触孔底部的蚀刻停止层。 通过使用光致抗蚀剂图案作为离子注入掩模，将杂质离子注入去除蚀刻停止层的接触孔的底部。

公开(公告)号：KR1020030037064A

公开(公告)日：2003-05-12

申请号：KR1020010068158

申请日：2001-11-02

Applicant: 삼성전자주식회사

Inventor： 박영래 ,  윤보언 ,  황홍규

IPC: H01L21/304

Abstract: PURPOSE: A carrier of chemical mechanical polishing equipment including a slurry feeding part is provided to prevent supplied polishing slurry from being unnecessarily wasted by installing the slurry feeding part in the outer circumference of a carrier body and by installing a gas outflow unit capable of supplying a gas curtain to the outer circumference of the slurry feeding part. CONSTITUTION: The carrier body(100) holds and rotates a wafer(200) to make the wafer contact the surface of a polishing pad(180). The slurry feeding part(160) supplies polishing slurry to a place near a contact surface between the wafer and the polishing pad, installed in a side part of the carrier body. A gas blower(300) provides the gas curtain for preventing the supplied polishing slurry from being pushed to the outside, installed in the outside of the outer circumference of the slurry feeding part in the side part of the carrier body.

Abstract translation: 目的：提供一种包括浆料供给部分的化学机械抛光设备的载体，以防止在载体主体的外周安装浆料供给部件并且安装能够提供 气幕到浆料进料部分的外周。 构成：承载体（100）保持和旋转晶片（200）以使晶片接触抛光垫（180）的表面。 浆料供给部（160）将抛光浆料供给到安装在载体主体的侧部的晶片与抛光垫之间的接触面附近的位置。 气体鼓风机（300）提供气幕，用于防止供应的抛光浆料被推到安装在载体主体的侧部中的浆料供给部分的外周的外侧。

公开(公告)号：KR100363093B1

公开(公告)日：2002-12-05

申请号：KR1020000043680

申请日：2000-07-28

Applicant: 삼성전자주식회사

Inventor： 남지원 ,  박기종 ,  황홍규 ,  배준식 ,  박영래 ,  김정엽 ,  윤보언 ,  하상록

IPC: H01L21/3105

Abstract: 반도체 소자의 층간 절연막 평탄화 방법을 제공한다. 본 발명은 복수개의 단위 셀들이 형성된 셀 블록들과 그 주위의 다른 영역을 포함하는 칩 영역이 복수개 형성된 반도체 기판의 전면에 상기 셀블록들 상의 고단차 영역과 다른 영역 상의 저단차 영역을 가지는 층간 절연막을 형성한다. 이어서, 상기 층간 절연막 상에 상기 고단차 영역을 노출시키는 셀 오픈 영역을 갖는 마스크 패턴을 형성 한 후, 이를 식각 마스크로 상기 고단차 영역을 부분 식각하여 고단차 영역과 저단차 영역의 단차를 줄인다. 상기 식각 마스크로 이용된 마스크 패턴을 제거한 후, 상기 부분식각된 고단차 영역과 저단차 영역의 층간 절연막을 화학기계적연마하여 평탄화한다. 특히, 본 발명은 상기 셀 오픈 영역의 모양이나 면적을 셀 블록별로 다르게 하거나, 하나의 셀 블록 내에서도 상기 셀 블록의 엣지로부터의 이격거리를 서로 다르게 형성하여 칩 영역의 전체에 걸쳐 연마 균일도를 향상시킬 수 있다.