公开(公告)号：KR1020020009972A

公开(公告)日：2002-02-02

申请号：KR1020000043680

申请日：2000-07-28

Applicant: 삼성전자주식회사

Inventor： 남지원 ,  박기종 ,  황홍규 ,  배준식 ,  박영래 ,  김정엽 ,  윤보언 ,  하상록

IPC: H01L21/3105

CPC classification number: H01L21/31056 ,  H01L21/31053 ,  H01L21/76819

Abstract: PURPOSE: A method for planarizing an interlayer dielectric of a semiconductor device is provided to improve polishing uniformity regarding the entire chip region in a chemical mechanical polishing(CMP) process, by forming cell open regions of different shapes or areas in every cell block or by making the cell open regions have different separation intervals from the edge of the cell blocks. CONSTITUTION: An interlayer dielectric has a high step region on cell blocks and a low step region on other region near the cell blocks. The interlayer dielectric is formed on the entire surface of a semiconductor substrate wherein the cell blocks having a plurality of unit cells and a plurality of chip regions including the other region near the cell blocks are formed. A mask pattern in which the shape and area of the cell open region exposing the high step region varies according to the cell blocks, is formed on the interlayer dielectric. The high step region is partially etched by using the mask pattern as an etch mask to improve step coverage of the high step region and the low step region. The mask pattern used as the etch mask is eliminated. A CMP process is performed regarding the interlayer dielectric in the partially-etched high and low step regions.

Abstract translation: 目的：提供一种用于平面化半导体器件的层间电介质的方法，以通过在每个电池块中形成不同形状或区域的电池开放区域或通过在每个电池块中形成不同形状或区域的电池开放区域来改善化学机械抛光（CMP）工艺中整个芯片区域的抛光均匀性 使细胞开放区域与细胞块的边缘具有不同的分离间隔。 构成：层间电介质在单元块上具有高的阶跃区域，在单元块附近的其它区域上具有低阶段区域。 层间电介质形成在半导体衬底的整个表面上，其中形成具有多个单元电池的单元块和包括靠近单元块的其它区域的多个芯片区域。 在层间电介质上形成掩模图案，其中暴露高阶区域的单元开放区域的形状和面积根据单元块而变化。 通过使用掩模图案作为蚀刻掩模来部分蚀刻高阶区域，以改善高阶区域和低阶区域的阶梯覆盖。 消除了用作蚀刻掩模的掩模图案。 对部分蚀刻的高阶和低阶区域中的层间电介质进行CMP工艺。

公开(公告)号：KR1020030094476A

公开(公告)日：2003-12-12

申请号：KR1020020031406

申请日：2002-06-04

Applicant: 삼성전자주식회사

Inventor： 남지원

IPC: H01L21/8242

Abstract: PURPOSE: A method for manufacturing a semiconductor memory device is provided to be capable of preventing the generation of particles when carrying out a planarization process, by effectively carrying out the planarization process at the predetermined portion located between a cell region and a peripheral region. CONSTITUTION: After defining a cell region and a peripheral region at a semiconductor substrate, MOS(Metal Oxide Semiconductor) transistors(110) are formed at the cell and peripheral region. Then, a capacitor(200) is formed at the upper portion of the MOS transistor of the cell region. After forming an interlayer dielectric(240) on the entire surface of the semiconductor substrate, an etching process is carried out at the interlayer dielectric of a buffer region, wherein the buffer region is located between the cell and peripheral region. After forming a planarization insulating layer(250) on the entire surface of the resultant structure, a planarization process is carried out at the planarization insulating layer.

Abstract translation: 目的：提供一种制造半导体存储器件的方法，通过在位于单元区域和外围区域之间的预定部分处有效地进行平坦化处理，能够在进行平坦化处理时防止粒子的产生。 构成：在半导体衬底上限定了单元区域和外围区域之后，在单元和外围区域形成MOS（金属氧化物半导体）晶体管110。 然后，在电池区域的MOS晶体管的上部形成有电容器（200）。 在半导体衬底的整个表面上形成层间电介质（240）之后，在缓冲区的层间电介质处进行蚀刻处理，其中缓冲区位于电池和周边区域之间。 在所得结构的整个表面上形成平坦化绝缘层（250）之后，在平坦化绝缘层处进行平坦化处理。

公开(公告)号：KR100363093B1

公开(公告)日：2002-12-05

申请号：KR1020000043680

申请日：2000-07-28

Applicant: 삼성전자주식회사

Inventor： 남지원 ,  박기종 ,  황홍규 ,  배준식 ,  박영래 ,  김정엽 ,  윤보언 ,  하상록

IPC: H01L21/3105

Abstract: 반도체 소자의 층간 절연막 평탄화 방법을 제공한다. 본 발명은 복수개의 단위 셀들이 형성된 셀 블록들과 그 주위의 다른 영역을 포함하는 칩 영역이 복수개 형성된 반도체 기판의 전면에 상기 셀블록들 상의 고단차 영역과 다른 영역 상의 저단차 영역을 가지는 층간 절연막을 형성한다. 이어서, 상기 층간 절연막 상에 상기 고단차 영역을 노출시키는 셀 오픈 영역을 갖는 마스크 패턴을 형성 한 후, 이를 식각 마스크로 상기 고단차 영역을 부분 식각하여 고단차 영역과 저단차 영역의 단차를 줄인다. 상기 식각 마스크로 이용된 마스크 패턴을 제거한 후, 상기 부분식각된 고단차 영역과 저단차 영역의 층간 절연막을 화학기계적연마하여 평탄화한다. 특히, 본 발명은 상기 셀 오픈 영역의 모양이나 면적을 셀 블록별로 다르게 하거나, 하나의 셀 블록 내에서도 상기 셀 블록의 엣지로부터의 이격거리를 서로 다르게 형성하여 칩 영역의 전체에 걸쳐 연마 균일도를 향상시킬 수 있다.

公开(公告)号：KR1020010046739A

公开(公告)日：2001-06-15

申请号：KR1019990050628

申请日：1999-11-15

Applicant: 삼성전자주식회사

Inventor： 남지원

IPC: H01L21/31

Abstract: PURPOSE: A method for planarizing an insulating layer of a semiconductor device is provided to make the slope in a step difference generation portion gentle by reducing a step difference on the insulating layer, and to prevent a notching problem between metal interconnections by guaranteeing process margin in a subsequent process such as a photolithography process for forming a contact. CONSTITUTION: An insulating layer(340) is deposited on a semiconductor substrate(300) including a structure(320) inducing a step difference. The insulating layer on the structure is planarized by a chemical mechanical polishing(CMP) process. The insulating layer is annealed and flowed.

Abstract translation: 目的：提供一种半导体器件的绝缘层的平坦化方法，通过减小绝缘层上的台阶差，使台阶差产生部分的坡度平缓，并且通过保证金属互连之间的切口问题，保证工艺裕度 诸如用于形成接触的光刻工艺的后续工艺。 构成：在半导体衬底（300）上沉积绝缘层（340），该绝缘层包括引起台阶差的结构（320）。 通过化学机械抛光（CMP）工艺将结构上的绝缘层平坦化。 绝缘层退火并流动。