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公开(公告)号：KR1020010017696A
公开(公告)日：2001-03-05
申请号：KR1019990033354
申请日：1999-08-13
Applicant: 삼성전자주식회사
IPC: H01L21/76
CPC classification number: H01L21/76229 , H01L21/31053 , H01L21/31055
Abstract: PURPOSE: A trench isolation method is provided to improve planarization of an isolating layer and overall planarization between the isolating layer and a semiconductor substrate, by etching an insulating material layer by a chemical mechanical polishing(CMP) process and a general wet or dry etching process. CONSTITUTION: After chemical mechanical polishing(CMP) blocking patterns(32) are formed on a semiconductor substrate(30), an anisotropical etching process is performed to form a trench(34a,34b) by using the CMP blocking patterns as a mask. An insulating material layer is applied as a shape for filling the trench while covering the CMP blocking patterns. The insulating material layer is firstly etched by a CMP process until the CMP blocking patterns starts to be exposed. The insulating material layer is secondly wet or dry etched until a predetermined thickness of the insulating material layer is left on the semiconductor substrate.
Abstract translation: 目的：通过化学机械抛光（CMP）工艺和一般的湿法或干法蚀刻工艺蚀刻绝缘材料层，提供沟槽隔离方法，以改善绝缘层的平面化和隔离层与半导体衬底之间的整体平坦化 。 构成：在半导体衬底（30）上形成化学机械抛光（CMP）阻挡图案（32）之后，通过使用CMP阻挡图案作为掩模，进行各向异性热蚀刻工艺以形成沟槽（34a，34b）。 施加绝缘材料层作为填充沟槽的形状，同时覆盖CMP阻挡图案。 首先通过CMP工艺蚀刻绝缘材料层，直到CMP阻挡图案开始曝光。 绝缘材料层被第二次湿式或干蚀刻，直到绝缘材料层的预定厚度留在半导体衬底上。
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公开(公告)号：KR100791345B1
公开(公告)日：2008-01-03
申请号：KR1020060097153
申请日：2006-10-02
Applicant: 삼성전자주식회사
IPC: H01L21/28
CPC classification number: H01L21/76804 , H01L21/76834 , H01L21/76889 , H01L23/5226 , H01L2924/0002 , H01L2924/00
Abstract: A semiconductor device including a recessed spherical silicide contact part is provided to prevent a metal silicide region from being chemically and physically damaged by forming a metal silicide region in a position lower than the surface of an interlayer dielectric. Isolation regions(120) are formed on a substrate(110). Source/drain regions(130) are formed near the isolation regions and the source/drain regions. A first interlayer dielectric(140) is formed on the substrate, the isolation regions and the source/drain regions. Contact pads(150) vertically penetrates the first interlayer dielectric to be electrically connected to the source/drain regions. A second interlayer dielectric(160) is formed on the first interlayer dielectric and the contact pads. A metal silicide region(170) is selectively formed on the contact pads, formed in a position lower than that surface of the first interlayer dielectric. Contact plugs(180) vertically penetrate the second interlayer dielectric to be electrically connected to the metal silicide region. A portion of the metal silicide region electrically connected to the contact plug is made of a rounded shape. The upper surface of the contact pad can be a concave shape. A barrier layer(185) can be formed between the contact plug and the second interlayer dielectric.
Abstract translation: 提供包括凹形球形硅化物接触部分的半导体器件，以通过在低于层间电介质的表面的位置形成金属硅化物区域来防止金属硅化物区域化学和物理损坏。 隔离区域（120）形成在基板（110）上。 源极/漏极区域（130）形成在隔离区域和源极/漏极区域附近。 在衬底，隔离区和源极/漏极区上形成第一层间电介质（140）。 接触焊盘（150）垂直地穿过第一层间电介质以电连接到源/漏区。 在第一层间电介质和接触焊盘上形成第二层间电介质（160）。 金属硅化物区域（170）选择性地形成在接触焊盘上，形成在比第一层间电介质的表面低的位置。 接触插塞（180）垂直穿过第二层间电介质以电连接到金属硅化物区域。 电连接到接触插塞的金属硅化物区域的一部分由圆形形成。 接触垫的上表面可以是凹形。 可以在接触插塞和第二层间电介质之间形成阻挡层（185）。
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公开(公告)号：KR1020020009972A
公开(公告)日：2002-02-02
申请号：KR1020000043680
申请日：2000-07-28
Applicant: 삼성전자주식회사
IPC: H01L21/3105
CPC classification number: H01L21/31056 , H01L21/31053 , H01L21/76819
Abstract: PURPOSE: A method for planarizing an interlayer dielectric of a semiconductor device is provided to improve polishing uniformity regarding the entire chip region in a chemical mechanical polishing(CMP) process, by forming cell open regions of different shapes or areas in every cell block or by making the cell open regions have different separation intervals from the edge of the cell blocks. CONSTITUTION: An interlayer dielectric has a high step region on cell blocks and a low step region on other region near the cell blocks. The interlayer dielectric is formed on the entire surface of a semiconductor substrate wherein the cell blocks having a plurality of unit cells and a plurality of chip regions including the other region near the cell blocks are formed. A mask pattern in which the shape and area of the cell open region exposing the high step region varies according to the cell blocks, is formed on the interlayer dielectric. The high step region is partially etched by using the mask pattern as an etch mask to improve step coverage of the high step region and the low step region. The mask pattern used as the etch mask is eliminated. A CMP process is performed regarding the interlayer dielectric in the partially-etched high and low step regions.
Abstract translation: 目的：提供一种用于平面化半导体器件的层间电介质的方法，以通过在每个电池块中形成不同形状或区域的电池开放区域或通过在每个电池块中形成不同形状或区域的电池开放区域来改善化学机械抛光（CMP）工艺中整个芯片区域的抛光均匀性 使细胞开放区域与细胞块的边缘具有不同的分离间隔。 构成：层间电介质在单元块上具有高的阶跃区域，在单元块附近的其它区域上具有低阶段区域。 层间电介质形成在半导体衬底的整个表面上，其中形成具有多个单元电池的单元块和包括靠近单元块的其它区域的多个芯片区域。 在层间电介质上形成掩模图案，其中暴露高阶区域的单元开放区域的形状和面积根据单元块而变化。 通过使用掩模图案作为蚀刻掩模来部分蚀刻高阶区域，以改善高阶区域和低阶区域的阶梯覆盖。 消除了用作蚀刻掩模的掩模图案。 对部分蚀刻的高阶和低阶区域中的层间电介质进行CMP工艺。
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公开(公告)号：KR1020090075347A
公开(公告)日：2009-07-08
申请号：KR1020080001171
申请日：2008-01-04
Applicant: 삼성전자주식회사
CPC classification number: B32B15/01 , B32B15/017 , B32B15/018 , H01L24/03 , H01L24/05 , H01L2224/02166 , H01L2224/04042 , H01L2224/05093 , H01L2224/05181 , H01L2224/05553 , H01L2224/05556 , H01L2224/05567 , H01L2224/05571 , H01L2224/48091 , H01L2224/48227 , H01L2924/00014 , H01L2924/0002 , H01L2924/01004 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01022 , H01L2924/01023 , H01L2924/01028 , H01L2924/01029 , H01L2924/01032 , H01L2924/01033 , H01L2924/01046 , H01L2924/0105 , H01L2924/01073 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01087 , H01L2924/014 , H01L2924/04941 , H01L2924/04953 , H01L2924/05042 , H01L2924/15311 , H01L2924/3025 , Y10T428/12528 , Y10T428/12701 , Y10T428/12736 , Y10T428/12882 , Y10T428/12896 , Y10T428/12931 , Y10T428/31678 , H01L2224/05552
Abstract: A bonding pad structure and method of manufacturing a bonding pad structure are provided to prevent oxidation of the lower pad of the bonding pad structure by make the lower pad not exposed to the outside when the upper pad is damaged. An upper pad(120) comprises a first area covered with a passivation film and a second part exposed from the passivation film(140). The lower pad is positioned under the first region of the upper pad in order not to be exposed through the second part. The lower pad(110) is electrically connected to the upper pad, and a contact member electrically connects the upper pad and the lower pad. The lower pad consecutively has a connected loop shape, and a contact member comprises a plurality of plug(130) which partly contact with the lower pad.
Abstract translation: 提供了一种焊盘结构和焊接结构的制造方法，用于当上焊盘损坏时，使下焊盘不暴露于外部，防止焊盘结构的下焊盘的氧化。 上焊盘（120）包括被钝化膜覆盖的第一区域和从钝化膜（140）露出的第二部分。 下垫位于上垫的第一区之下，以便不通过第二部露出。 下焊盘（110）电连接到上焊盘，并且接触部件电连接上焊盘和下焊盘。 下垫连续地具有连接的环形，并且接触构件包括与下垫部分接触的多个塞子（130）。
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公开(公告)号：KR100343146B1
公开(公告)日：2002-07-05
申请号：KR1020000065049
申请日：2000-11-02
Applicant: 삼성전자주식회사
IPC: H01L21/336
Abstract: 게이트 전극용 도전층을 필드산화막에 의해 리세스(recess) 된 활성영역에 다마신 구조 형성되는 반도체 소자 및 그 형성방법을 설명한다. 본 발명에 의하면, 활성영역에서는 게이트전극용 도전층이 형성되고 비활성영역에서는 게이트 전극용 도전층이 형성되지 않기 때문에 후속공정에서 층간절연막을 증착할 때, 층간절연막의 두께를 줄여서 층간절연막 내부에서 보이드(void)가 발생하는 것을 억제하고, 활성영역의 바닥면에 선택적 성장에 의한 폴리실리콘막을 다시 성장시키기 때문에 활성영역의 바닥면에서 발생되는 마이크로 스크래치(micro scratch), 피팅(pitting) 및 스트링거의 영향을 최소화시킬 수 있다.
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Patent Agency Ranking
公开(公告)号：KR1020020034635A
公开(公告)日：2002-05-09
申请号：KR1020000065049
申请日：2000-11-02
Applicant: 삼성전자주식회사
IPC: H01L21/336
CPC classification number: H01L21/76897 , H01L21/28123 , H01L21/76832 , H01L21/76834 , H01L21/76837 , H01L21/823437 , H01L21/823481
Abstract: PURPOSE: A method for fabricating a semiconductor device having a gate electrode of a damascene structure is provided to control generation of a void in an interlayer dielectric deposited after a gate line is formed, and to minimize a defect like a micro scratch, pitting or stringer. CONSTITUTION: An insulation layer for a filed oxide layer(106) is formed in a trench formed by patterning a pad oxide layer and a polishing stop layer formed on a semiconductor substrate(100). A chemical mechanical polishing(CMP) process for forming a shallow trench isolation(STI) is performed to define an active region and an inactive region. The polishing stop layer and the pad oxide layer in the active region are removed to form a gate oxide layer. A conductive layer for a gate electrode is deposited. A CMP process is performed to make the conductive layer for the gate electrode have a damascene structure by using the filed oxide layer in the inactive region as a polishing stop layer. A silicide layer and a gate upper insulation layer are stacked and patterned on the substrate to form respective gates in the active and inactive regions. A gate line having a spacer is formed on the sidewall of the gate stack, and a polysilicon layer(120) is grown on the bottom surface of the active region by a selective growth method. An etch stop layer(122) is formed by a blanket etch method. An interlayer dielectric is formed on the semiconductor substrate having the etch stop layer and is etched back.
Abstract translation: 目的：提供一种用于制造具有镶嵌结构的栅电极的半导体器件的方法，以控制在栅极线形成之后沉积的层间电介质中的空隙的产生，并且使诸如微划痕，点蚀或纵向的缺陷最小化 。 构成：在通过图案化形成在半导体衬底（100）上的衬垫氧化物层和抛光停止层形成的沟槽中形成用于氧化物层（106）的绝缘层。 执行用于形成浅沟槽隔离（STI）的化学机械抛光（CMP）工艺以限定有源区和非活性区。 有源区中的抛光停止层和焊盘氧化物层被去除以形成栅极氧化物层。 沉积用于栅电极的导电层。 通过使用非活性区域中的氧化物层作为抛光停止层，进行CMP工艺以使栅电极的导电层具有镶嵌结构。 硅化物层和栅极上绝缘层在衬底上堆叠和图案化以在有源区域和非活性区域中形成相应的栅极。 具有间隔物的栅极线形成在栅叠层的侧壁上，并且通过选择生长法在活性区的底表面上生长多晶硅层（120）。 通过覆盖蚀刻方法形成蚀刻停止层（122）。 在具有蚀刻停止层的半导体衬底上形成层间电介质并被回蚀刻。
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公开(公告)号：KR1020010097949A
公开(公告)日：2001-11-08
申请号：KR1020000022470
申请日：2000-04-27
Applicant: 삼성전자주식회사
Inventor： 황홍규
IPC: H01L21/31
Abstract: 반도체 소자의 커패시터를 덮는 절연막 평탄화 방법을 개시한다. 본 발명의 일 관점은, 반도체 기판의 셀 영역(cell region) 상에 형성된 커패시터의 상부 전극을 덮어 커패시터의 높이에 의해서 표면 단차를 가지는 절연막을 형성한다. 절연막 상에 연마 종료막을 형성한다. 연마 종료막 및 절연막의 상부 전극을 덮는 고단차 부분을 선택적으로 부분 식각하여 절연막의 고단차 부분의 두께를 감소시킨다. 절연막의 저단차 부분 상의 연마 종료막이 드러날 때까지 절연막 상을 화학 기계적 연마한다. 연마 종료막의 잔류하는 부분을 제거한다.
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公开(公告)号：KR1020020044737A
公开(公告)日：2002-06-19
申请号：KR1020000073806
申请日：2000-12-06
Applicant: 삼성전자주식회사
IPC: H01L21/302
CPC classification number: B24B53/017 , H01L21/67046
Abstract: PURPOSE: A CMP(Chemical Mechanical Polishing) equipment including a conditioning cleaner is provided to minimize micro-scratches of a polishing pad by removing various polishing residues remaining between diamond pellets on the surface of a conditioning disc by using a brush on a cleaner. CONSTITUTION: A CMP equipment comprises a polishing pad(44), a conditioner(50) including a conditioning disc(52) for conditioning the polishing pad(44), and a conditioning parking bath(54) having a conditioning cleaner(80) for cleansing the conditioning disc(52). The conditioning cleaner(80) further includes a brush part made of a multiple of brushes for removing various polishing residues from the conditioning disc(52) by contacting and pressurizing the brush part to the surface of the conditioning disc(52), thereby reducing micro-scratches of the polishing pad(44).
Abstract translation: 目的：提供包括调理清洁剂的CMP（化学机械抛光）设备，通过使用清洁剂上的刷子除去在调理盘表面上的金刚石颗粒之间残留的各种抛光残渣，以最小化抛光垫的微划痕。 构造：CMP设备包括抛光垫（44），包括用于调节抛光垫（44）的调节盘（52）的调节器（50）和具有调节清洁器（80）的调节停车浴（54） 清洁调理盘（52）。 调理清洁器（80）还包括由多个刷子制成的刷子部分，用于通过使刷部件接触和加压到调节盘（52）的表面来从调节盘（52）中除去各种抛光残留物，从而减少微调 - 抛光垫（44）。
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公开(公告)号：KR1020010111745A
公开(公告)日：2001-12-20
申请号：KR1020000032393
申请日：2000-06-13
Applicant: 삼성전자주식회사
IPC: H01L21/31
Abstract: 커패시터 영역과 코아영역의 단차문제를 완화하면서, 커패시터 영역의 가장자리에 형성된 커패시터가 식각이나 화학기계적 연마공정으로 인해 손상받는 것을 억제할 수 있는 손상방지용 절연막을 이용한 반도체 소자의 제조방법에 관해 개시한다. 이를 위해 본 발명은, 커패시터영역과 코아영역에 단차가 형성된 반도체 기판을 준비하는 단계와, 상기 반도체기판 위에 층간절연막을 형성하는 단계와, 상기 층간절연막 위에 손상방지용 절연막을 형성하는 단계와, 상기 커패시터 영역의 층간절연막이 노출되도록 상기 손상방지용 절연막을 화학기계적 연마로 평탄화하는 단계와, 상기 코아영역의 손상방지용 절연막이 제거될 때까지 습식식각을 진행하는 단계를 구비하는 것을 특징으로 하는 커패시터 영역의 손상을 방지하기 위한 반도체 소자의 제조방법을 제공한다.
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公开(公告)号：KR100297736B1
公开(公告)日：2001-11-01
申请号：KR1019990033354
申请日：1999-08-13
Applicant: 삼성전자주식회사
IPC: H01L21/76
CPC classification number: H01L21/76229 , H01L21/31053 , H01L21/31055
Abstract: 본발명은반도체소자의제조방법에관한것으로, 특히웨이퍼전체에걸쳐평탄화를이룰수 있는반도체소자의트렌치소자분리방법에관한것이다. 반도체기판상에 CMP 차단층을도포한 후이를패터닝하여소자분리영역을노출시키는창을갖는모양의 CMP 차단패턴을형성한다. CMP 차단패턴을마스크로한 식각을행하여트렌치를형성한다. 트렌치를완전히채움과동시에 CMP 차단패턴들을덮도록절연물질층을도포한다. CMP 차단패턴들이노출될때까지 CMP 공정을진행하여절연물질층을 1차적으로제거한다. 반도체기판표면으로부터소정의돌출된두께, 즉소정의돌출된두께는 CMP 차단패턴들을제거한후 게이트산화막형성전의중간처리단계시 제거되는절연물질층의두께에해당하는두께가남을때까지절연물질층을통상의습식또는건식식각으로 2차적으로제거한다. CMP 차단패턴들을제거한다.
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