-
公开(公告)号：KR100264396B1
公开(公告)日：2000-08-16
申请号：KR1019980010830
申请日：1998-03-27
Applicant: 한국과학기술원
IPC: H01J1/30
Abstract: PURPOSE: A method for manufacturing a lateral field emission display device is provided to form a cathode pattern, an anode pattern, and a gate pattern as one mask by using an electron beam lithography process. CONSTITUTION: A conductive layer is formed on a substrate including an insulating layer. The conductive layer is formed as the first conductive layer pattern, the second conductive layer pattern, and the third conductive layer pattern by performing a lithography process. The first conductive layer pattern forms a cathode electrode(11). The second conductive layer pattern forms an anode electrode(12). The third conductive layer pattern forms a gate electrode(13,13').
Abstract translation: 目的：提供一种用于制造横向场发射显示装置的方法，以通过使用电子束光刻工艺形成阴极图案，阳极图案和作为一个掩模的栅极图案。 构成：在包括绝缘层的基板上形成导电层。 通过进行光刻工艺，导电层形成为第一导电层图案，第二导电层图案和第三导电层图案。 第一导电层图案形成阴极电极（11）。 第二导电层图案形成阳极电极（12）。 第三导电层图案形成栅电极（13,13'）。
-
公开(公告)号：KR1019990076137A
公开(公告)日：1999-10-15
申请号：KR1019980010830
申请日：1998-03-27
Applicant: 한국과학기술원
IPC: H01J1/30
Abstract: 본 발명은 전자선 리소그래피를 이용하여 한 장의 마스크로 캐소드, 에노드, 게이트 전극을 형성시킬 수 있어, 제조공정을 단순화시킨 측면형 전계방출소자의 제조방법을 제공하는데 그 목적이 있다.
본 발명에 따르면, 전계방출소자의 제조방법에 있어서, 그 표면에 절연막이 형성된 기판상에 전도막을 형성하는 단계와; 전자선 리소그래피 공정을 통해 상기 전도막을 캐소드 전극 형성을 위한 제1전도막 패턴과, 에노드 전극 형성을 위한 제2전도막 패턴 및, 게이트 전극 형성을 위한 제3전도막 패턴으로 형성하는 단계 및: 상기 캐소드, 에노드, 게이트 전극의 팁을 미세 간격으로 형성하기 위해 상기 형성된 패턴에 열 산화를 수행하는 단계를 포함하며, 상기 제1전도막 내지 제3전도막의 패턴 형상은, 상기 캐소드 전극의 제1전도막과 상기 에노드 전극의 제2전도막이 상호 대향되고, 상기 게이트 전극의 제3전도막은 상호 대향되게 한 쌍을 구비하되, 상기 제1전도막과 상기 제2전도막의 접점은 상기 후속 단계를 통해 임의의 수 나노 스케일의 간격이 형성될 수 있도록 미세 구조로 형성하고, 상기 한 쌍의 제3전도막은 가능한 한 상기 제1전도막과 제2전도막의 접점에 가깝도 록 형성하는 것을 특징으로 하는 전계방출소자의 제조방법이 제공된다.-
公开(公告)号：KR1020100027635A
公开(公告)日：2010-03-11
申请号：KR1020080086629
申请日：2008-09-03
Applicant: 한국과학기술원
CPC classification number: H03K23/544 , H03K3/35613 , H03K21/10
Abstract: PURPOSE: A CML type D flip-flop and a frequency odd divider using the same are provided to easily expand a structure by adding the D flip-flops. CONSTITUTION: A first NMOS transistor(NM1) is connected between a first node(N1) and a second node(N2). A second NMOS transistor(NM2) is connected between a third node(N3) and a fourth node(N4). A third NMOS transistor(NM3) is connected between a fifth node(N5) and the second node. A fourth NMOS transistor(NM4) is connected between the fifth node and the fourth node. A fifth NMOS transistor(NM5) is connected between the third node and the fifth node. A sixth NMOS transistor is connected between the first node and the fifth node.
Abstract translation: 目的：提供CML D型触发器和使用其的频率奇数分频器，以通过添加D触发器来容易地扩展结构。 构成：第一NMOS晶体管（NM1）连接在第一节点（N1）和第二节点（N2）之间。 第二NMOS晶体管（NM2）连接在第三节点（N3）和第四节点（N4）之间。 第三NMOS晶体管（NM3）连接在第五节点（N5）和第二节点之间。 第四NMOS晶体管（NM4）连接在第五节点和第四节点之间。 第五NMOS晶体管（NM5）连接在第三节点和第五节点之间。 第六NMOS晶体管连接在第一节点和第五节点之间。
-
公开(公告)号：KR100405963B1
公开(公告)日：2003-11-14
申请号：KR1020010036850
申请日：2001-06-27
IPC: H01L27/10
Abstract: PURPOSE: A minimum channel memory device is provided to use a minimum channel device as a memory device by forming a side gate of relatively small work function on the side surface of a main gate and by performing a memory operation while using an inversion layer and the side gate formed on the side gate. CONSTITUTION: An oxide layer(24) is formed on a semiconductor substrate(30). The main gate(21) is formed on the oxide layer. An insulation layer(25) surrounds the right and left side surfaces of the main gate. The first and second gates(22,23) have work function different than that of the main gate, respectively formed on the right and left side surfaces of the main gate while the insulation layer is used as a medium. A source/drain is formed in the substrate under the first and second gates. The inversion layer(26,27) is formed in the substrate under the first and second gates, adjacent to the source/drain.
Abstract translation: 目的：通过在主栅极的侧面上形成功函数相对较小的侧栅极并通过在使用反转层的同时执行存储器操作来提供最小沟道存储器件以使用最小沟道器件作为存储器件， 在侧门上形成侧门。 构成：在半导体衬底（30）上形成氧化层（24）。 主栅极（21）形成在氧化物层上。 绝缘层（25）围绕主门的右侧和左侧表面。 第一和第二栅极（22,23）的功函数不同于主栅极的功函数，分别形成在主栅极的右侧和左侧表面上，而绝缘层用作介质。 在第一和第二栅极之下的衬底中形成源极/漏极。 反转层（26,27）形成在第一和第二栅极下方的衬底中，与源极/漏极相邻。
-
公开(公告)号：KR1020030000747A
公开(公告)日：2003-01-06
申请号：KR1020010036850
申请日：2001-06-27
IPC: H01L27/10
Abstract: PURPOSE: A minimum channel memory device is provided to use a minimum channel device as a memory device by forming a side gate of relatively small work function on the side surface of a main gate and by performing a memory operation while using an inversion layer and the side gate formed on the side gate. CONSTITUTION: An oxide layer(24) is formed on a semiconductor substrate(30). The main gate(21) is formed on the oxide layer. An insulation layer(25) surrounds the right and left side surfaces of the main gate. The first and second gates(22,23) have work function different than that of the main gate, respectively formed on the right and left side surfaces of the main gate while the insulation layer is used as a medium. A source/drain is formed in the substrate under the first and second gates. The inversion layer(26,27) is formed in the substrate under the first and second gates, adjacent to the source/drain.
Abstract translation: 目的：提供最小通道存储器件以通过在主栅极的侧表面上形成具有相对较小功函数的侧栅，并且通过在使用反转层的同时执行存储器操作来使用最小通道器件作为存储器件，并且 侧门形成在侧门上。 构成：在半导体衬底（30）上形成氧化物层（24）。 主栅极（21）形成在氧化物层上。 绝缘层（25）围绕主门的左右侧表面。 第一和第二栅极（22,23）具有与主栅极不同的功函数，分别形成在主栅极的左右侧面上，而绝缘层用作介质。 源极/漏极在第一和第二栅极之下的衬底中形成。 反转层（26,27）形成在第一和第二栅极下方的衬底中，邻近源极/漏极。
-
Patent Agency Ranking
公开(公告)号：KR1020000073779A
公开(公告)日：2000-12-05
申请号：KR1019990017281
申请日：1999-05-14
Applicant: 한국과학기술원 , 신성전자공업 주식회사
IPC: H03B5/30
CPC classification number: H01L27/0629 , H03J2200/10 , H03L1/026
Abstract: PURPOSE: A capacitor block for temperature adaptation and a temperature compensated crystal oscillator using thereof are provided to perform the error compensation of the resonance frequency according to the temperature variation efficiently and to solve the non-monotonic while the silicon area is deceased. CONSTITUTION: A temperature compensated crystal oscillator using capacitor block for temperature adaptation comprises a crystal oscillator(60), a temperature sensing circuit(61), an analog-digital converter(62), a controller(63), a memory(64) and a decoder(65). The crystal oscillator(60) outputs the variable resonance frequency according to the temperature and load capacitor. The temperature sensing circuit(61) senses the around temperature of the crystal oscillator(60) and outputs the electrical signal. The analog-digital converter(62) converts the sensed signal to digital type. The controller(63) reads a unit capacitor switch control code by using the present temperature sensed from the analog-digital convertor(62) and the temperature area boundary value stored at the memory(64), controls the unit capacitor and varies the load capacitance of the crystal oscillator(60). The memory(64) stores the unit capacitor switch control code according to the temperature. The decoder(65) provides the switch control code provided from the controller(63) to two capacitor bank(66,67).
Abstract translation: 目的：提供一种用于温度适应的电容器块和使用其的温度补偿晶体振荡器，以有效地根据温度变化执行谐振频率的误差补偿，并且在硅面积下降时解决非单调谐波。 构成：使用电容器块进行温度补偿的温度补偿晶体振荡器包括晶体振荡器（60），温度感测电路（61），模拟数字转换器（62），控制器（63），存储器（64）和 解码器（65）。 晶体振荡器（60）根据温度和负载电容输出可变谐振频率。 温度检测电路（61）感测晶体振荡器（60）的周围温度并输出电信号。 模拟数字转换器（62）将感测到的信号转换为数字类型。 控制器（63）通过使用从模拟数字转换器（62）感测的当前温度和存储在存储器（64）中的温度区域边界值来读取单位电容器开关控制代码，控制单位电容器并改变负载电容 的晶体振荡器（60）。 存储器（64）根据温度存储单位电容器开关控制代码。 解码器（65）将从控制器（63）提供的开关控制代码提供给两个电容器组（66,67）。
-
公开(公告)号：KR1020000065949A
公开(公告)日：2000-11-15
申请号：KR1019990012742
申请日：1999-04-12
Applicant: 한국과학기술원
IPC: H01L21/334
Abstract: PURPOSE: A method for manufacturing a microscopic channel device is provided to improve a mobility of a carrier and to minimize a variation of a threshold voltage, by using a side surface gate having a different work function than a main gate so that a channel under the side surface channel functions as a thin source/drain region and increases a doping of a channel region. CONSTITUTION: A p+ polycrystalline silicon inner gate(505) is defined by using a microscopic patterning technology on a p- substrate(501,503). After an oxidation layer is formed on the resultant structure, a n+ polycrystalline silicon side surface gate(507) is formed by intervening the inner gate and oxidation layer. P¬0 halo ions are injected into both side surfaces of the side surface gate, and source/drain n+ ions are injected.
Abstract translation: 目的：提供一种用于制造微通道器件的方法，以通过使用具有与主栅极不同的功函数的侧表面栅极来改善载流子的迁移率并最小化阈值电压的变化，使得在 侧面通道用作薄的源极/漏极区域并增加沟道区域的掺杂。 构成：通过在p-衬底上使用显微图案化技术来限定p +多晶硅内门（505）（501,503）。 在所得结构上形成氧化层之后，通过插入内部栅极和氧化层形成n +多晶硅侧表面栅极（507）。 将P_0卤素离子注入侧表面栅极的两个侧表面，并注入源极/漏极n +离子。
-
公开(公告)号：KR100271207B1
公开(公告)日：2000-11-01
申请号：KR1019980007771
申请日：1998-03-09
Applicant: 한국과학기술원
IPC: H01L29/78
Abstract: PURPOSE: A high speed and low electric power FET with a subsidiary MOSFET is provided to be capable of implementing a fast operation by lowering a threshold voltage in transient of logic values since a source of a subsidiary transistor is connected to a body of a main transistor and a gate is connected to a source or a drain of the main transistor to apply a bias to the body of the main transistor, and of reducing leakage current without limiting operational voltage by maintaining high threshold voltage. CONSTITUTION: Two MOS transistors are respectively used as a main transistor(21) having general functions and a subsidiary transistor(22) for applying bias to a body portion of the main transistor(21). A source of the subsidiary transistor(22) is connected to a gate of the main transistor(21), and a gate of the subsidiary transistor(22) is connected to a drain or a source of the main transistor(21).
Abstract translation: 目的：提供具有辅助MOSFET的高速和低功率FET，以便能够通过降低逻辑值瞬态中的阈值电压来实现快速操作，因为辅助晶体管的源极连接到主晶体管的主体 并且栅极连接到主晶体管的源极或漏极，以向主晶体管的主体施加偏压，并且通过保持高阈值电压来减小漏电流而不限制工作电压。 构成：两个MOS晶体管分别用作具有一般功能的主晶体管（21）和用于向主晶体管（21）的主体部分施加偏压的辅助晶体管（22）。 辅助晶体管（22）的源极连接到主晶体管（21）的栅极，并且辅助晶体管（22）的栅极连接到主晶体管（21）的漏极或源极。
-
公开(公告)号：KR1020000008634A
公开(公告)日：2000-02-07
申请号：KR1019980028534
申请日：1998-07-15
Applicant: 한국과학기술원
IPC: H01L21/336 , B82Y40/00
CPC classification number: B82Y10/00 , H01L21/28273 , H01L29/42324 , H01L29/66825 , H01L29/7883 , Y10S438/962
Abstract: PURPOSE: A nonvolatile memory formation method using a nano crystal is provided to uniformly and exactly form fine nano crystal and improve a reproducibility by using increase of etching ratio and oxidant ratio at grain boundary. CONSTITUTION: The method comprises the steps of forming a tunneling insulator(204) and an amorphous silicon layer(206) on a silicon substrate(202); transforming the amorphous silicon layer to a polycrystalline silicon layer(210); etching the polycrystalline silicon layer(210) using seco or light etching, thereby forming uniform nano crystal(212) having a high density due to increase of etching ratio at grain boundary(211) of the polycrystalline silicon; forming an interlayer dielectric(214) on the nano crystal(212); and forming a gate(216) on the interlayer dielectric.
Abstract translation: 目的：提供使用纳米晶体的非易失性存储器形成方法，以均匀且精确地形成精细的纳米晶体，并且通过使用晶界处的蚀刻比和氧化剂比例的增加来提高再现性。 构成：该方法包括在硅衬底（202）上形成隧道绝缘体（204）和非晶硅层（206）的步骤; 将所述非晶硅层转化为多晶硅层（210）; 用多次硅蚀刻多晶硅层（210），由于多晶硅的晶界处的蚀刻比（211）增加而形成均匀的具有高密度的纳米晶体（212）; 在所述纳米晶体（212）上形成层间电介质（214）; 以及在所述层间电介质上形成栅极（216）。
-
公开(公告)号：KR1019990074292A
公开(公告)日：1999-10-05
申请号：KR1019980007771
申请日：1998-03-09
Applicant: 한국과학기술원
IPC: H01L29/78
Abstract: 본 발명은 주 트랜지스터의 바디 부위에 바이어스를 가함으로써, 논리값(logic value)의 전이시 문턱 전압(threshold voltage)을 낮춰 빠른 동작이 이루어지도록 하고, 그 외에는 높은 문턱전압을 유지하여 누설전류가 작도록 하며, 동작 전압에 제한 없이 동작되도록 한 전계효과트랜지스터를 제공하는데 그 목적이 있다.
본 발명에 따르면, 반도체의 바디 부위 내에 형성되며, 소오스, 드레인, 상기 소오스와 드레인간 형성되는 채널 부위, 그리고 상기 채널 부위 상에 접속된 게이트를 구비한 제1트랜지스터와; 반도체의 바디 부위 내에 형성되며, 소오스, 드레인, 상기 소오스와 드레인간 형성되는 채널 부위, 그리고 상기 채널 부위 상에 접속된 게이트를 구비한 제2트랜지스터를 포함하며; 상기 제2트랜지스터의 소오스는 상기 제1트랜지스터의 바디 부위에 연결되고, 상기 제2트랜지스터의 드레인은 상기 제1트랜지스터의 게이트에 연결되며, 상기 제2트랜지스터의 게이트는 상기 제1트랜지스터의 드레인 또는 소오스에 연결된 것을 특징으로 하는 반도체 장치가 제공된다.
-
-
-
-
-
-
-
-
-
Search Results
23
records
(took 0.02 seconds)
