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公开(公告)号：KR1019930006732B1
公开(公告)日：1993-07-23
申请号：KR1019910007454
申请日：1991-05-08
Applicant: 한국전자통신연구원
IPC: H01L27/04
CPC classification number: H01L28/20 , H01L21/743 , H01L21/76248 , H01L21/76251 , H01L23/535 , H01L28/40 , H01L2924/0002 , Y10S148/012 , Y10S148/135 , H01L2924/00
Abstract: The method comprises (a) forming a 1st insulation film (27) on the seed wafer (21), (b) forming a 2nd insulation film (29) on (27) and defining substrate contact (28), (c) depositing a 1st polycrystalline silicon (30) on (28), (d) forming fine pattern on (30) to define electric structural body (31), (e) growing or depositing insulation film (32) for (31), (f) depositing a 2nd polycrystalline silicon layer (33) and grinding (33) into mirror plane to remove surface unevenness, (g) forming insulation film (35) on handle wafer (36) and joining the mirror plane (34b) with the film (35), and (h) grinding the wafer (21) into thin film until the film (27) appears from the rear side (21a) of (21).
Abstract translation: 该方法包括：（a）在种子晶片（21）上形成第一绝缘膜（27），（b）在（27）上形成第二绝缘膜（29）并限定衬底触点（28），（c） （28）上的第一多晶硅（30），（d）在（30）上形成精细图案以限定电结构体（31），（e）生长或沉积用于（31）的绝缘膜（32），（f） 第二多晶硅层（33）和研磨（33）成镜面以去除表面凹凸，（g）在手柄晶片（36）上形成绝缘膜（35）并将镜面（34b）与膜（35）接合， ，和（h）将晶片（21）研磨成薄膜，直到膜（27）从（21）的后侧（21a）出现。
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公开(公告)号：KR1019930003858B1
公开(公告)日：1993-05-14
申请号：KR1019890006542
申请日：1989-05-16
Applicant: 한국전자통신연구원
IPC: H01L21/22
Abstract: The method for increasing the boron concentration of the isolation layer (field oxide film) under portion to have a low threshold voltage and a low junction capacitance comprises the steps of forming a SiO2 film (6) and silicon nitride film (6) on a Si substrte (5) to define an active region by active masking process, etching the film (7,6) and substrate (5) to form grooves for field region, implanting impurity ions thereinto to form an ion implantation layer (8) at the field region to form a SiO2 film (9) and P+ region (10) by thermal oxidation, depositing a polysilicon layer (11) thereon to form a poly silicon oxide film (12), etching-back the film (12) to remove the films (7)(6) to expose the substrate and growing a silicon epitaxial layer (13) thereon by selective epitaxy process.
Abstract translation: 用于提高部分下具有低阈值电压和低结电容的隔离层（场氧化物膜）的硼浓度的方法包括在Si上形成SiO 2膜（6）和氮化硅膜（6）的步骤 （5）以通过有源屏蔽工艺限定有源区，蚀刻膜（7,6）和衬底（5）以形成用于场区的沟槽，将杂质离子注入其中以在场处形成离子注入层（8） 区域，通过热氧化形成SiO 2膜（9）和P +区域（10），在其上沉积多晶硅层（11）以形成多晶硅氧化膜（12），蚀刻膜（12）以去除膜 （7）（6），以通过选择性外延工艺露出衬底并在其上生长硅外延层（13）。
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Patent Agency Ranking
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公开(公告)号：KR1019910008126B1
公开(公告)日：1991-10-10
申请号：KR1019890006543
申请日：1989-05-16
Applicant: 한국전자통신연구원
Abstract: The transistor including a polysilicon self-aligned source/ drain and double diffused drain using residual sidewall silicon oxide is formed by: (a) performing an active region and polysilicon gate on silicon substrate (45), followed by depositing silicon oxide (45,46) and silicon nitride (48); (b) depositing a PSG (45) with 500nm thickness on silicon substrate, the PSG thickness of gate part is half than that of other part; (c) removing the only PSG (49) layer of polysilicon gate (47) by reactive ion etching; (d) selective growing the polysilicon oxide (53) on gate part (55) after etching the PSG (50) on silicon substrate and silicon oxide (52) on polysilicon gate (47).
Abstract translation: 使用剩余侧壁氧化硅的多晶硅自对准源极/漏极和双扩散漏极的晶体管通过：（a）在硅衬底（45）上执行有源区和多晶硅栅极，然后沉积氧化硅（45,46 ）和氮化硅（48）; （b）在硅衬底上沉积厚度为500nm的PSG（45），栅极部分的PSG厚度为其他部分的一半; （c）通过反应离子蚀刻去除多晶硅栅极（47）的唯一PSG（49）层; （d）在蚀刻硅衬底上的PSG（50）和多晶硅栅极（47）上的氧化硅（52）之后，选择性地生长栅极部分（55）上的多晶硅氧化物（53）。
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