公开(公告)号：WO2002095762A3

公开(公告)日：2002-11-28

申请号：PCT/US2002/004779

申请日：2002-02-19

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： WANG, Zhigang ,  FASTOW, Richard ,  HADDAD, Sameer ,  PARK, Sheung-Hee ,  CHANG, Chi

IPC: G11C16/10

Abstract: A source resistor or a positive voltage is couples to the source and a negative bias voltage is applied at the substance or p-well of flash memory cells for enhanced efficiency during programming and/or during an APDE (Automatic Program Disturb after Erase) process for a flash memory device. Furthermore, in a system and method for programming the flash memory device, a flash memory cell of the array of multiple flash memory cells is selected to be programmed. A control gate programming voltage is applied to the control gate of the selected flash memory cell, and a bit line programming voltage is applied to the drain of the selected flash memory cell via the common bit line terminal to which the drain of the selected flash memory cell is connected. In a system and method for performing an APDE (Automatic Program Disturb after Erase) process, a column of flash memory cells of the array of multiple flash memory cells is selected to be erase-corrected. A bit line APDE (Automatic program Disturb after Erase) voltage is applied to the common bit line terminal corresponding to the selected column of flash memory cells. A control gate APDE (Automatic Program Disturb after Erase) voltage is applied to the respective control gate of each flash memory cell of the selected column of flash memory cells. Alternatively, the source is coupled to the control gate for each flash memory cell in a self-biasing configuration such that the control gate APDE voltage is not applied to the respective control gate of each flash memory cell of the selected column of flash memory cells.

公开(公告)号：WO1996013057A2

公开(公告)日：1996-05-02

申请号：PCT/US1995012901

申请日：1995-09-29

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： ADVANCED MICRO DEVICES, INC. ,  FANG, Hao ,  HADDAD, Sameer ,  CHANG, Chi

IPC: H01L00/00

CPC classification number: H01L27/0251 ,  H01L27/115

Abstract: An improved non-volatile memory device (10) is provided, in which the threshold voltage variations (Vts) and transconductance degradation are significantly reduced. The NVM (10) includes protection structure (200) for limiting the process induced damage incurred during the manufacturing process. The protection structure (200) is utilized to provide reliable and stable dielectrical characteristics for the NVM device (10). The protection structure (200) is easy to implement and will not affect the conventional NVM (10) performance.

Abstract translation: 提供了一种改进的非易失性存储器件（10），其中阈值电压变化（Vts）和跨导退化明显降低。 NVM（10）包括用于限制在制造过程中产生的过程引起的损坏的保护结构（200）。 保护结构（200）用于为NVM装置（10）提供可靠和稳定的介电特性。 保护结构（200）易于实现，不会影响传统的NVM（10）性能。

公开(公告)号：EP1019914A1

公开(公告)日：2000-07-19

申请号：EP98919745.4

申请日：1998-04-10

Applicant: ADVANCED MICRO DEVICES INC. ,  FUJITSU LIMITED

Inventor： CHEN, Pau-Ling ,  VAN BUSKIRK, Michael ,  HOLLMER, Shane, Charles ,  LE, Bing, Quang ,  KAWAMURA, Shoichi ,  HU, Chung-You ,  SUN, Yu ,  HADDAD, Sameer ,  CHANG, Chi

IPC: G11C16/04

CPC classification number: G11C16/0483

Abstract: A series select transistor and a source select transistor are connected in series at the end of a NAND string of floating gate data storage transistors. The floating gates, the series select gate, and the source select gate are all preferably formed of polysilicon. The same tunnel oxide layer is used as gate oxide for the series select transistor and source select transistor as well as for the floating gate data storage transistors. Two layers of polysilicon in the series select gate and the source select gates are tied together. The series select transistor is tied to the last transistor in the NAND string. The source select transistor is tied to the array Vss supply. In order to program inhibit a specific NAND cell during the programming of another NAND cell, the gate of the series select transistor is raised to Vcc, while the gate of the source select transistor is held to ground. The two transistors in series are able to withstand a much higher voltage at the end of the NAND string without causing gated-diode junction or oxide breakdown in either the series or the source select transistor.

公开(公告)号：EP0835509A1

公开(公告)日：1998-04-15

申请号：EP96922505.0

申请日：1996-06-18

Applicant: ADVANCED MICRO DEVICES INC.

Inventor： HADDAD, Sameer ,  CHANG, Chi ,  LIU, David, K., Y.

IPC: G11C16

CPC classification number: G11C16/10

Abstract: Disclosed herein is a channel hot-carrier page write method including an array of stacked gate flash EEPROM memory cells operating in a very low energy programming mode permitting page writing of 1024 bits within a 20-100νS programming interval. Internal programming voltage levels are derived from on-chip circuits, such as charge pumps (272), operated from a single +Vcc source. In a preferred embodiment, a cache memory (262) buffers data transfers between a computer bus (264) and the page oriented storage array (252). In another embodiment, core doping is increased in the channel and drain regions to enhance hot carrier injection and to lower the programming drain voltage. The stacked floating gate structure is shown to exhibit a high programming efficiency in a range from 10?-6 to 10-4¿ at drain voltages below 5.2VDC. In another embodiment AC components of the programming current are minimized by precharging a common source line at the start of a programming cycle.

公开(公告)号：EP2064756B1

公开(公告)日：2016-05-04

申请号：EP07838014.4

申请日：2007-09-10

Applicant: ADVANCED MICRO DEVICES, INC. ,  Spansion LLC

Inventor： PANGRLE, Suzette, K. ,  AVANZINO, Steven ,  HADDAD, Sameer ,  VANBUSKIRK, Michael ,  RATHOR, Manuj ,  XIE, James ,  SONG, Kevin ,  MARRIAN, Christie ,  CHOO, Bryan ,  WANG, Fei ,  SHIELDS, Jeffrey, A.

IPC: H01L45/00

CPC classification number: H01L45/04 ,  H01L27/2436 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/1633 ,  H01L45/1675 ,  H01L45/1683

公开(公告)号：EP1673781B1

公开(公告)日：2007-07-25

申请号：EP04784309.9

申请日：2004-09-16

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： RANDOLPH, Mark ,  HADDAD, Sameer ,  THURGATE, Timothy ,  FASTOW, Richard

IPC: G11C7/18 ,  G11C16/04

CPC classification number: H01L27/11568 ,  G11C16/0483 ,  H01L27/115 ,  H01L27/11521

Abstract: A memory cell array (50) comprises a two dimensional array of memory cells (52) fabricated on a semiconductor substrate (54). The memory cells (52) are arranged in a plurality of rows defining a row direction (67) and a plurality columns defining a column direction (69). Each column of memory cells (52) comprising a plurality of alternating channel regions (58) and source/drain regions (64). A conductive interconnect (72) is positioned above each source/drain region (64) and coupled to only one other source/drain region (64). The one other source/drain region (64) is in a second column that is adjacent to the column. The conductive interconnects (64) are positioned such that every other conductive interconnect (64) connects to the adjacent column to a right side of the column and every other conductive interconnect connects to adjacent column to the left side of the column. A plurality of source/drain control lines (70) extends between adjacent columns of memory cells (52) and electrically couple to each conductive interconnect (72) that couples between the adjacent columns.

公开(公告)号：EP1673781A1

公开(公告)日：2006-06-28

申请号：EP04784309.9

申请日：2004-09-16

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： RANDOLPH, Mark ,  HADDAD, Sameer ,  THURGATE, Timothy ,  FASTOW, Richard

IPC: G11C7/18 ,  G11C16/04

CPC classification number: H01L27/11568 ,  G11C16/0483 ,  H01L27/115 ,  H01L27/11521

Abstract: A memory cell array (50) comprises a two dimensional array of memory cells (52) fabricated on a semiconductor substrate (54). The memory cells (52) are arranged in a plurality of rows defining a row direction (67) and a plurality columns defining a column direction (69). Each column of memory cells (52) comprising a plurality of alternating channel regions (58) and source/drain regions (64). A conductive interconnect (72) is positioned above each source/drain region (64) and coupled to only one other source/drain region (64). The one other source/drain region (64) is in a second column that is adjacent to the column. The conductive interconnects (64) are positioned such that every other conductive interconnect (64) connects to the adjacent column to a right side of the column and every other conductive interconnect connects to adjacent column to the left side of the column. A plurality of source/drain control lines (70) extends between adjacent columns of memory cells (52) and electrically couple to each conductive interconnect (72) that couples between the adjacent columns.

公开(公告)号：EP1402535A1

公开(公告)日：2004-03-31

申请号：EP01274195.5

申请日：2001-11-14

Applicant: ADVANCED MICRO DEVICES INC.

Inventor： FASTOW, Richard, M. ,  HADDAD, Sameer ,  CLEVELAND, Lee

IPC: G11C16/34

CPC classification number: G11C16/3422 ,  G11C16/344 ,  G11C16/3445

Abstract: A technique is provided for reducing column leakage in a flash EEPROM device (10) during an erase verification process, thereby preventing false verifies. The technique has application in NOR arrays or other types of arrays in which a number of cells (100) are connected in parallel. The technique operates by reducing the leakage of the unselected cells in parallel to the selected cell being verified, thereby preventing false verifies. The technique can also be used in conjunction with other techniques for reducing column leakage, such as soft programming, automatic programming disturb erase (APDE), or various other Vth compacting schemes.

公开(公告)号：EP2064756A2

公开(公告)日：2009-06-03

申请号：EP07838014.4

申请日：2007-09-10

Applicant: ADVANCED MICRO DEVICES, INC. ,  Spansion LLC

Inventor： PANGRLE, Suzette, K. ,  AVANZINO, Steven ,  HADDAD, Sameer ,  VANBUSKIRK, Michael ,  RATHOR, Manuj ,  XIE, James ,  SONG, Kevin ,  MARRIAN, Christie ,  CHOO, Bryan ,  WANG, Fei ,  SHIELDS, Jeffrey, A.

IPC: H01L45/00

CPC classification number: H01L45/04 ,  H01L27/2436 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/1633 ,  H01L45/1675 ,  H01L45/1683

Abstract: A present method of fabricating a memory device includes the steps of providing a dielectric layer (110), providing an opening (1 12) in the dielectric layer (110), providing a first conductive body ( 116A) in the opening (112), providing a switching body ( 118A) in the opening (112), the first conductive body ( 116A) and switching body (118A) filling the opening (112), and providing a second conductive body (120A) over the switching body (118A). In an alternate embodiment, a second dielectric layer (150) is provided over the first-mentioned dielectric layer (110), and the switching body (156A) is provided in an opening (152) in the second dielectric layer (150).

公开(公告)号：EP1745511A1

公开(公告)日：2007-01-24

申请号：EP05713458.7

申请日：2005-02-11

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： QIAN, Weidon ,  RAMSBEY, Mark, T. ,  YANG, Jean, Yee-Mei ,  HADDAD, Sameer

IPC: H01L27/115 ,  H01L21/8247

CPC classification number: H01L27/115 ,  H01L27/11568

Abstract: The present invention pertains to implementing a dual poly process (500) in forming a transistor based memory device (600). The process allows buried bitlines (662) to be formed with less energy and to shallower depths than conventional bitlines to save resources and space, and to improve Vt roll-off. Oxide materials (670, 674) are also formed over the buried bitlines (662) to improve (e.g., increase) a breakdown voltage between the bitlines (662) and wordlines (678), thus allowing for greater discrimination between programming and erasing charges and more reliable resulting data storage. The process (500) also facilitates a reduction in buried bitline width (666) and thus allows bitlines (662) to be formed closer together. As a result, more devices can be 'packed' within the same or a smaller area.