公开(公告)号：WO2003063168A2

公开(公告)日：2003-07-31

申请号：PCT/US2002/040823

申请日：2002-12-17

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： CHEN, Pau-Ling ,  VANBUSKIRK, Michael, A. ,  SUN, Yu

IPC: G11C

CPC classification number: G11C16/28 ,  G11C16/0491

Abstract: A system (600, 800) is disclosed for producing an indication (679) of the logical state of a flash memory cell (866) for virtual ground flash memory (640) operations. The system (600, 800) comprises a bit line precharge and hold circuit (660, 855) which is operable to apply and maintain a source terminal voltage (859) ( e.g. , about 0 volts, ground) to a bit line (850) associated with the source terminal (857) of a cell adjacent (856) to the cell which is sensed (866) during a read operation, wherein the applied source terminal voltage is substantially the same as the bit line virtual ground voltage (869) applied to the source terminal bit line (860) of the selected memory cell (866) to be sensed. The system (600, 800) also includes a drain bit line circuit (650, 875) operable to generate a drain terminal voltage (615, 815) for a drain terminal (868) of a selected memory cell (866) to be sensed. The system (600, 800) further includes a selective bit line decode circuit (652) which is operable to select the bit lines (860, 870) of a memory cell (866) to be sensed and the bit line (850) of an adjacent cell (856), and a core cell sensing circuit (695, 890) which is operable to sense a core cell sense current (675) at a bit line associated with a source terminal (867) of the selected memory cell (866) to be sensed during memory read operations, and produce an indication (679) of the flash memory cell logical state, which is substantially independent of charge sharing leakage current to an adjacent cell.

Abstract translation: 公开了一种用于产生用于虚拟接地闪存（640）操作的闪存单元（866）的逻辑状态的指示（679）的系统（600,800）。 该系统（600,800）包括位线预充电和保持电路（660,855），其可操作以施加并保持源端电压（859）（例如，约0伏，地） 到与在读取操作期间被感测（866）的单元相邻（856）的单元的源极端子（857）相关联的位线（850），其中所施加的源极端子电压实质上与位线 施加到所选择的存储器单元（866）的源极端位线（860）以被感测的虚拟接地电压（869）。 该系统（600,800）还包括漏极位线电路（650,875），该漏极位线电路可操作以产生用于将被感测的所选存储器单元（866）的漏极端子（868）的漏极端子电压（615,815）。 该系统（600,800）还包括选择性位线解码电路（652），其可操作以选择要被感测的存储器单元（866）的位线（860,870）以及 相邻单元（856）以及核心单元感测电路（695,890），所述核心单元感测电路可操作以在与所选存储器单元（866）的源极端子（867）相关联的位线处感测核心单元感测电流（675） 以在存储器读取操作期间被感测，并且产生闪存单元逻辑状态的指示（679），其基本上独立于到相邻单元的电荷共享漏电流。

公开(公告)号：WO2003058709A3

公开(公告)日：2003-07-17

申请号：PCT/US2002/039739

申请日：2002-12-11

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： KIM, UnSoon ,  SUN, Yu ,  KINOSHITA, Hiroyuki ,  CHANG, Kuo-Tung ,  SACHAR, Harpreet, K. ,  CHANG, Mark, S.

IPC: H01L21/762

Abstract: A method for performing shallow trench isolation during semiconductor fabrication that improves trench corner rounding is disclosed. The method includes etching trenches into a silicon substrate (24) between active regions, and performing a double liner oxidation process and on the trenches. The method further includes performing a double sacrificial oxidation process and on the active regions, wherein corners (35) of the trenches are substantially rounded by the four oxidation processes.

公开(公告)号：WO2003058709A2

公开(公告)日：2003-07-17

申请号：PCT/US2002/039739

申请日：2002-12-11

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： KIM, UnSoon ,  SUN, Yu ,  KINOSHITA, Hiroyuki ,  CHANG, Kuo-Tung ,  SACHAR, Harpreet, K. ,  CHANG, Mark, S.

IPC: H01L21/762

CPC classification number: H01L21/76235

Abstract: A method for performing shallow trench isolation during semiconductor fabrication that improves trench corner rounding is disclosed. The method includes etching trenches (34) into a silicon substrate (24) between active regions (30), and performing a double liner oxidation process (56) and (60) on the trenches (34). The method further includes performing a double sacrificial oxidation process (72) and (76) on the active regions (30), wherein corners (35) of the trenches (34) are substantially rounded by the four oxidation processes.

Abstract translation: 公开了一种用于在半导体制造期间进行浅沟槽隔离的方法，其改善沟槽角圆化。 该方法包括将沟槽（34）蚀刻到有源区域（30）之间的硅衬底（24）中，并且在沟槽（34）上执行双衬层氧化工艺（56）和（60）。 该方法还包括在有源区域（30）上执行双重牺牲氧化工艺（72）和（76），其中沟槽（34）的拐角（35）通过四个氧化工艺基本上被圆化。

公开(公告)号：EP1250714A1

公开(公告)日：2002-10-23

申请号：EP00984473.9

申请日：2000-12-13

Applicant: ADVANCED MICRO DEVICES INC.

Inventor： PHAM, Tuan, Duc ,  RAMSBEY, Mark, T. ,  SUN, Yu ,  CHANG, Chi

IPC: H01L21/762 ,  H01L21/8239

CPC classification number: H01L21/76202 ,  H01L21/76224 ,  H01L27/1052 ,  Y10S438/981

Abstract: An improved flash memory device, which has shallow trench isolation in the periphery region and LOCOS isolation in the core region is provided. A hard mask is used first to create the shallow trench isolation. The LOCOS isolation is then created. Subsequent etching is used to remove stringers. The flash memory is able to use shallow trench isolation to limit encroachment. The flash memory may also have a nitridated tunnel oxide layer. A hard mask is used to prevent nitride contamination of the gate oxide layer.

公开(公告)号：EP1436833A2

公开(公告)日：2004-07-14

申请号：EP02800870.4

申请日：2002-09-30

Applicant: ADVANCED MICRO DEVICES INC.

Inventor： SUN, Yu ,  VAN BUSKIRK, Michael, A. ,  RAMSBEY, Mark, T.

IPC: H01L21/8246 ,  H01L27/115 ,  H01L27/105

CPC classification number: H01L27/11568 ,  H01L27/115

Abstract: A method of forming a non-volatile semiconductor memory device, involving forming a charge trapping dielectric (114) over a substrate (112); forming a first set of memory cell gates (116) over the charge trapping dielectric (114) in a core region; forming a conformal insulation material layer (118) around the first set of memory cell gates (116); and forming a second set of memory cell gates (122) in the core region, wherein each memory cell gate of the second set of memory cell gates (122) is adjacent to at least one memory cell gate of the first set of memory cell gates (116), each memory cell gate of the first set of memory cell gates (116) is adjacent at least one memory cell gate of the second set of memory cell gates (122), and the conformal insulation material layer (118) is positioned between each adjacent memory cell gate is disclosed.

公开(公告)号：EP1019914A1

公开(公告)日：2000-07-19

申请号：EP98919745.4

申请日：1998-04-10

Applicant: ADVANCED MICRO DEVICES INC. ,  FUJITSU LIMITED

Inventor： CHEN, Pau-Ling ,  VAN BUSKIRK, Michael ,  HOLLMER, Shane, Charles ,  LE, Bing, Quang ,  KAWAMURA, Shoichi ,  HU, Chung-You ,  SUN, Yu ,  HADDAD, Sameer ,  CHANG, Chi

IPC: G11C16/04

CPC classification number: G11C16/0483

Abstract: A series select transistor and a source select transistor are connected in series at the end of a NAND string of floating gate data storage transistors. The floating gates, the series select gate, and the source select gate are all preferably formed of polysilicon. The same tunnel oxide layer is used as gate oxide for the series select transistor and source select transistor as well as for the floating gate data storage transistors. Two layers of polysilicon in the series select gate and the source select gates are tied together. The series select transistor is tied to the last transistor in the NAND string. The source select transistor is tied to the array Vss supply. In order to program inhibit a specific NAND cell during the programming of another NAND cell, the gate of the series select transistor is raised to Vcc, while the gate of the source select transistor is held to ground. The two transistors in series are able to withstand a much higher voltage at the end of the NAND string without causing gated-diode junction or oxide breakdown in either the series or the source select transistor.

公开(公告)号：EP1459374A2

公开(公告)日：2004-09-22

申请号：EP02806155.4

申请日：2002-12-11

Applicant: ADVANCED MICRO DEVICES INC.

Inventor： KIM, UnSoon ,  SUN, Yu ,  KINOSHITA, Hiroyuki ,  CHANG, Kuo-Tung ,  SACHAR, Harpreet, K. ,  CHANG, Mark, S.

IPC: H01L21/762 ,  H01L21/311 ,  H01L21/316

CPC classification number: H01L21/76235

Abstract: A method for performing shallow trench isolation during semiconductor fabrication that improves trench corner rounding is disclosed. The method includes etching trenches into a silicon substrate (24) between active regions, and performing a double liner oxidation process and on the trenches. The method further includes performing a double sacrificial oxidation process and on the active regions, wherein corners (35) of the trenches are substantially rounded by the four oxidation processes.

公开(公告)号：EP1435114A2

公开(公告)日：2004-07-07

申请号：EP02773624.8

申请日：2002-09-27

Applicant: ADVANCED MICRO DEVICES INC.

Inventor： RAMSBEY, Mark, T. ,  SUN, Yu ,  CHANG, Chi

IPC: H01L27/105

CPC classification number: H01L27/11526 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/115 ,  H01L27/11531

Abstract: Processes for doping and saliciding word lines (20) in a virtual ground array flash memory device without causing shorting between bit lines (26) are disclosed. According to one aspect, word lines (20) are doped prior to patterning the poly layer from which the word lines (20) are formed in the core region. Thereby, the poly layer protects the substrate between the word lines (20) from doping that could cause shorting between bit lines (26). According to another aspect, word lines (20) are exposed while spacer material, dielectric, or like material protects the substrate between word lines (20). The spacer material or dielectric prevents the substrate from becoming salicided in a manner that, like doping, could cause shorting between bit lines (26). Disclosed are virtual ground array flash memory devices with doped and salicided word lines (20), but no shorting between bit lines (26) even in virtual ground arrays where there are no oxide island isolation regions (28) between bit lines (26).

Abstract translation: 公开了在虚拟接地阵列闪存器件中掺杂和助化字线（20）而不引起位线（26）之间短路的过程。 根据一个方面，在图案化在核心区域中形成字线（20）的多晶层之前，掺杂字线（20）。 从而，多晶硅层保护字线（20）之间的衬底免受可能导致位线（26）之间短路的掺杂。 根据另一方面，字线（20）被暴露，而间隔材料，电介质或类似材料保护字线（20）之间的衬底。 间隔物材料或电介质以类似于掺杂的方式防止衬底变成硅化物，从而可能导致位线（26）之间短路。 公开了具有掺杂和硅化字线（20）的虚拟接地阵列闪存器件，但即使在位线（26）之间不存在氧化物岛隔离区域（28）的虚拟接地阵列中，位线（26）之间也不短路。

公开(公告)号：EP1264342A1

公开(公告)日：2002-12-11

申请号：EP01916603.2

申请日：2001-03-12

Applicant: ADVANCED MICRO DEVICES INC.

Inventor： SHIELDS, Jeffrey, A. ,  PHAM, Tuan, D. ,  RAMSBEY, Mark, T. ,  SUN, Yu ,  HUI, Angela, T. ,  CHAN, Maria, Chow

IPC: H01L21/8247 ,  H01L21/8246

CPC classification number: H01L27/11568 ,  H01L27/11526 ,  H01L27/11531

Abstract: In a two-step spacer fabrication process for a non-volatile memory device (1), a thin oxide layer (12) is deposited on a wafer substrate (3) leaving a gap in the core (24) of the non-volatile memory device (1). Implantation and/or oxide-nitride-oxide removal can be accomplished through this gap. After implantation, a second spacer (13) is deposited. After the second spacer deposition, a periphery spacer etch is performed. By the above method, a spacer is formed.

Abstract translation: 在用于非易失性存储器件的两步间隔件制造工艺中，薄的氧化物层沉积在晶片衬底上，在非易失性存储器件的芯中留下间隙。 可通过该间隙实现植入和/或氧化氮化物 - 氧化物去除。 植入后，沉积第二间隔物。 在第二间隔物沉积之后，执行外围间隔物蚀刻。 通过上述方法，形成间隔物。

公开(公告)号：EP1222690A1

公开(公告)日：2002-07-17

申请号：EP00967129.8

申请日：2000-09-29

Applicant: ADVANCED MICRO DEVICES INC.

Inventor： HSAIO, Tommy, C. ,  RAMSBEY, Mark, T. ,  SUN, Yu

IPC: H01L21/8247 ,  H01L27/105

CPC classification number: H01L27/11526 ,  H01L27/11534 ,  H01L27/11543 ,  Y10S438/951

Abstract: Improved dimensional accuracy of the gate electrode structure in the peripheral circuitry region of a semiconductor device is achieved by reducing ARC loss during photoresist stripping associated with plural mask formation in the core memory cell region during patterning and ion implantations. Embodiments include sequentially etching the stacked gate electrode structure in the core memory cell region, photoresist stripping and etching to form the gate electrode structure in the peripheral circuitry region. Subsequently, plural maskings and ion implantations are implemented in the core memory cell region with attendant photoresist strippings.