公开(公告)号：JPH08330329A

公开(公告)日：1996-12-13

申请号：JP13513295

申请日：1995-06-01

Applicant: MATSUSHITA ELECTRONICS CORP

Inventor： UEDA TETSUZO ,  UEDA DAISUKE

IPC: H01L29/41 ,  H01L21/338 ,  H01L29/47 ,  H01L29/812 ,  H01L29/872

Abstract: PURPOSE: To provide an FET transistor in which uneven recess etching is eliminated on the under side of a gate electrode while reducing the source-gate leak current. CONSTITUTION: A channel layer 11, an intrinsic semiconductor layer 12 and a heavily doped surface contact layer 13 are formed sequentially on a semiinsulating substrate 10 followed by deposition of an insulating film 14 having a first opening 14a. A photoresist 15 having a second opening 15a is then deposited on the insulating film 14 and the semiinsulating substrate 10 is subjected to first time etching using the insulating film 14 as a mask thus making a first recess 13a. Subsequently, the insulating film 14 is etched using the photoresist 15 as a mask to enlarge the first opening 14a and the semiinsulating substrate 10 is subjected to second time etching using the photoresist 15 as a mask thus making a second recess in the surface part of the semiinsulating substrate 10. Finally, a gate electrode is formed in the second recess of the semiinsulating substrate 10.

公开(公告)号：JP2530933B2

公开(公告)日：1996-09-04

申请号：JP9479390

申请日：1990-04-10

Applicant: MATSUSHITA ELECTRONICS CORP

Inventor： UEDA TETSUZO ,  MYANAGA KAZUTSUNE

IPC: H01L21/60 ,  H01L21/338 ,  H01L29/812

公开(公告)号：JPH10163114A

公开(公告)日：1998-06-19

申请号：JP31910296

申请日：1996-11-29

Applicant: MATSUSHITA ELECTRONICS CORP

Inventor： YURI MASAAKI ,  UEDA TETSUZO ,  BABA TAKAAKI

IPC: H01L29/12 ,  H01L21/20 ,  H01L21/203 ,  H01L21/205 ,  H01S5/323

Abstract: PROBLEM TO BE SOLVED: To homogenize a lead oxide layer and improve the reproducibility, by forming this lead oxide layer on a single crystal substrate, a first GaN crystal within specified temp. range and a second GaN crystal within specified temp. range. SOLUTION: Using a sputtering apparatus, a lead oxide layer 2 is formed on a sapphire-made single crystal substrate 1, and GaN target is sputtered in a substrate temp. range of O to 900 deg.C in an N atmosphere to form a first GaN crystal 4 which is them heated at 900-2000 deg.C in an ammonia atmosphere to form a second GaN crystal 5. Thus it is possible to homogenize the lead oxide layer 5 and form a p-n junction diode at a good reproducibility over the entire surface of the lead oxide layer 2.

公开(公告)号：JPH03292746A

公开(公告)日：1991-12-24

申请号：JP9479290

申请日：1990-04-10

Applicant: MATSUSHITA ELECTRONICS CORP

Inventor： UEDA TETSUZO ,  MIYANAGA KAZUTSUNE

IPC: H01L21/60 ,  H01L21/338 ,  H01L29/812

Abstract: PURPOSE:To obtain a field-effect transistor, in which the peeling of a bonding pad is hardly generated, by a method wherein at least one part of the surface of a semiconductor substrate is formed into a roughened form and a gate metal film is formed on the roughened part of the surface in such a way as to correspond to the roughened form. CONSTITUTION:A spacer insulating film 4 consisting of silicon dioxide is evenly applied on a gallium-arsenic substrate 1 by a chemical deposition method. After then, a square part only arranged in a lattice type in the surface of the substrate 1 is etched, recesses and projections are formed and a gate metal film 2, which is formed into a form a conformed to the recesses and projections and consists of Ti and Al, is applied and formed on the recesses and projections by a vacuum deposition method. Then, a surface protective film 5 consisting of silicon dioxide is applied and formed on the substrate 1 and the film 2, a perforating work is performed with a hydrofluoric acid and after then, a wiring metal film 3 consisting of Ti, Pt and Au is deposited in a vacuum on the film 2 to obtain a field-effect transistor.

公开(公告)号：JPH1154438A

公开(公告)日：1999-02-26

申请号：JP20567397

申请日：1997-07-31

Applicant: MATSUSHITA ELECTRONICS CORP

Inventor： YURI MASAAKI ,  UEDA TETSUZO ,  BABA TAKAAKI

IPC: H01L29/20 ,  C30B25/02 ,  H01L21/20 ,  H01L21/203 ,  H01L21/205 ,  H01L33/32 ,  H01L33/00

Abstract: PROBLEM TO BE SOLVED: To form a cubic-system nitride semiconductor layer of good crystallinity on a substrate, by nitriding one surface of a cubic-system semiconductor layer comprising aluminum, and forming a cubic-system nitride semiconductor layer on the surface. SOLUTION: By heating a substrate 1, in a molecular beam epitaxy device, and a irradiation with As molecular beam, an oxide present on the surface of the substrate 1 is removed. Then, by supplying Ga and Al, a semiconductor layer 2 of AlGaAs is formed. Then, irradiation with dimethylhydrazine is started to begin surface-nitriding of the semiconductor layer 2, and RED pattern representing a crystal state on the surface of a semiconductor layer 2 is monitored with a reflective high-speed electron diffraction device (RHEED), and when the RED pattern representing presence of AlGaAs changes to that representing presence of AlGaN, Ga is supplied in addition to the dimethylhydrazine, for growth of a cubic-system nitride semiconductor layer 3 constituted of GaN.

公开(公告)号：JP2530932B2

公开(公告)日：1996-09-04

申请号：JP9479290

申请日：1990-04-10

Applicant: MATSUSHITA ELECTRONICS CORP

Inventor： UEDA TETSUZO ,  MYANAGA KAZUTSUNE

IPC: H01L21/60 ,  H01L21/338 ,  H01L29/812

公开(公告)号：JPH07273292A

公开(公告)日：1995-10-20

申请号：JP6333794

申请日：1994-03-31

Applicant: MATSUSHITA ELECTRONICS CORP

Inventor： UEDA TETSUZO ,  TANAKA TAKESHI ,  UEDA DAISUKE

IPC: H01F17/00 ,  H01L21/822 ,  H01L27/04

Abstract: PURPOSE:To obtain a semiconductor integrated circuit in which an inductor which has a large inductance value and a small series resistance value is formed in a small area part on a semiconductor substrate. CONSTITUTION:A metal interconnection 4 is formed on a semiconductor substrate 1. Oxide films 3, 5 which contain iron are arranged at the lower part, the left side, the right side and the upper part of the metal interconnection 4 so as to come into direct contact. Consequently, an induced electromotive force becomes large when a current is made to flow to the metal interconnection 4. As a result, an inductance value can be increased as compared with a case in which the oxide films 3, 5 do not exist. In addition, the total length of the metal interconnection 4 can be limited to be short, the resistance value of the metal interconnection 4 can be reduced, and the metal interconnection can be formed in a small area part on the semiconductor substrate 1.

公开(公告)号：JPH03292747A

公开(公告)日：1991-12-24

申请号：JP9479390

申请日：1990-04-10

Applicant: MATSUSHITA ELECTRONICS CORP

Inventor： UEDA TETSUZO ,  MIYANAGA KAZUTSUNE

IPC: H01L21/60 ,  H01L21/338 ,  H01L29/812

Abstract: PURPOSE:To prevent the peeling of a bonding pad from being generated by a method wherein a metal film, which is one part of the bonding pad part and is alloyed or made compatible with the surface of a semiconductor substrate, is provided on the surface of the substrate. CONSTITUTION:A spacer insulating film 5 consisting of silicon dioxide and an alloyed or compatible metal precurson film 2, which consists of AuGe and Au and is a bonding pad part, are applied on a gallium-arsenic substrate 1 by vacuum deposition and are heat-treated. The ohmic metal film 2 is alloyed or made compatible with the surface of the substrate 1 by the heat treatment. Gate metal films 3, which are made to penetrate the film 5 and consist of Ti and Al, are formed and are applied on the substrate by vacuum deposition. Then, a surface protective film 6, which consists of silicon dioxide, is applied on the substrate 1, the alloyed or compatible metal film 2, the films 3 and the film 5 by a thermal CVD method, the film 6 is subjected to perforating work with a hydrofluoric acid, a wiring metal film 4 is applied on the films 3 by vacuum deposition and a field-effect transistor is obtained.