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    1.
    发明专利
    未知

    公开(公告)号：DE19751294A1

    公开(公告)日：1998-06-04

    申请号：DE19751294

    申请日：1997-11-19

    Applicant: MATSUSHITA ELECTRONICS CORP

    Inventor： YURI MASAAKI ,  UEDA TETSUZO ,  BABA TAKAAKI

    IPC: H01L29/12 ,  H01L21/20 ,  H01L21/203 ,  H01L21/205 ,  H01S5/323

    Abstract: To present a manufacturing method of semiconductor device capable of forming a homogeneous and highly reproducible gallium nitride crystal, comprising the steps of forming a zinc oxide layer on a monocrystalline substrate, forming a first gallium nitride crystal in a temperature range from 0 DEG C. to 900 DEG C., and forming a second gallium nitride crystal in a temperature range from 900 DEG C. to 2000 DEG C.

    PRODUCTION OF GALLIUM NITRIDE CRYSTAL
    4.
    发明专利
    PRODUCTION OF GALLIUM NITRIDE CRYSTAL 失效

    公开(公告)号：JPH10287497A

    公开(公告)日：1998-10-27

    申请号：JP9067497

    申请日：1997-04-09

    Applicant: MATSUSHITA ELECTRONICS CORP

    Inventor： YURI MASAAKI ,  UEDA TETSUZO ,  BABA TAKAAKI

    IPC: C30B29/38 ,  H01L21/20 ,  H01L21/205 ,  H01L29/12 ,  H01S5/00 ,  H01S5/323 ,  H01S3/18

    Abstract: PROBLEM TO BE SOLVED: To make a crystal defect such as a crystal dislocation caused at the time of heteroepitaxial growth produced not on the side of a gallium nitride but on the side of a single crystal silicon thin film and obtain a thick-film gallium nitride crystal excellent in crystallinity by successively forming an amorphous silicon dioxide thin film, a single crystal silicon thin film and gallium nitride on a silicon substrate. SOLUTION: Oxygen ions are implanted onto a silicon substrate 1 and the resultant silicon substrate 1 is then heat-treated at, e.g. 1,320 deg.C to form an amorphous silicon dioxide thin film 2 on the silicon substrate 1 and a single crystal silicon thin film 3 thereon. An amorphous gallium nitride 4 is then formed on the single crystal silicon thin film 3 by a halide vapor-phase epitaxy(VPE) method for regulating the temperature of the substrate 1 to, e.g. 600 deg.C, feeding HCl gas through a metallic Ga surface and reacting the formed gallium chloride with NH3 . A single crystal gallium nitride 5 is further formed thereon by the halide VPE method for regulating the substrate temperature to, e.g. 1,000 deg.C.

    PRODUCTION OF GALLIUM NITRIDE CRYSTAL
    5.
    发明专利
    PRODUCTION OF GALLIUM NITRIDE CRYSTAL 失效

    公开(公告)号：JPH10287496A

    公开(公告)日：1998-10-27

    申请号：JP9067397

    申请日：1997-04-09

    Applicant: MATSUSHITA ELECTRONICS CORP

    Inventor： YURI MASAAKI ,  UEDA TETSUZO ,  BABA TAKAAKI

    IPC: C30B29/38 ,  C30B25/02 ,  C30B25/18 ,  H01L21/205 ,  H01L29/12 ,  H01S5/00 ,  H01S5/323 ,  H01S3/18

    Abstract: PROBLEM TO BE SOLVED: To obtain a gallium nitride crystal excellent in flatness and crystallinity by heating a substrate in a gas atmosphere containing Ga, then forming the first gallium nitride on the substrate and subsequently forming the second gallium nitride on the first gallium nitride at a temperature higher than that for forming the first gallium nitride. SOLUTION: For example, N2 gas is introduced through a GaCl3 surface heated at the melting point or above and a substrate 1 (e.g. a silicon substrate) is then heated at, e.g. 700 deg.C in a gas atmosphere containing Ga to form growth nuclei 2 composed of, e.g. GaCl2 . The first gallium nitride 3 which is amorphous is formed on the growth nuclei 2 by, e.g. a halide vapor-phase epitaxy(VPE) method for regulating the temperature of the substrate 1 to 600 deg.C and reacting the GaCl3 with NH3 . The second gallium nitride 4 which is a single crystal is then formed on the first gallium nitride 3 at a higher temperature (e.g. 1,000 deg.C) than that for forming the first gallium nitride 3 on the first gallium nitride 3 by, e.g. the halide VPE method.

    PROGRAMMABLE INTEGRATED CIRCUIT
    7.
    发明专利
    PROGRAMMABLE INTEGRATED CIRCUIT 失效

    公开(公告)号：JPH11205125A

    公开(公告)日：1999-07-30

    申请号：JP244298

    申请日：1998-01-08

    Applicant: MATSUSHITA ELECTRONICS CORP ,  ONOE TAKAO ,  SHIRAKAWA ISAO

    Inventor： ONOE TAKAO ,  ASARI KOJI ,  HONDA TOSHIYUKI ,  SHIRAKAWA ISAO ,  OTSUKI TATSUO ,  BABA TAKAAKI

    IPC: G11C14/00 ,  G11C11/22 ,  H03K19/173 ,  H03K19/177

    Abstract: PROBLEM TO BE SOLVED: To provide a programmable integrated circuit provided with efficient memory constitution for storing and loading the data for logic constitution of a programmable logic element. SOLUTION: This programmable integrated circuit incorporates the programmable logic element 101 and a ferroelectric memory 109. The data for the logic constitution are loaded from the ferroelectric memory 101 to the programmable logic element 101 when a power source is turned ON and thereafter, the ferroelectric memory 101 is used as a random access memory. Immediately before turning the power source OFF, the data for the logic constitution of the programmable logic element 101 are written back to the ferroelectric memory 101. The ferroelectric memory 101 holds the data for the logic constitution at the time of non-energizing as a nonvolatile memory.

    IMAGE INPUT DISPLAY
    8.
    发明专利
    IMAGE INPUT DISPLAY 失效

    公开(公告)号：JPH11136587A

    公开(公告)日：1999-05-21

    申请号：JP30149297

    申请日：1997-11-04

    Applicant: MATSUSHITA ELECTRONICS CORP

    Inventor： TOUMON MOTOJI ,  CHIKAMURA TAKAO ,  ITO KUNIO ,  BABA TAKAAKI ,  TAKIGAWA SHINICHI

    IPC: H04N5/225 ,  H04N5/335 ,  H04N5/357 ,  H04N5/363 ,  H04N5/372 ,  H04N5/376 ,  H04N5/378

    Abstract: PROBLEM TO BE SOLVED: To miniaturize an image input device by mounting a charge coupled device to which an image is inputted and a circuit which drives the charge coupled device on the same substrate as a semiconductor chip. SOLUTION: On the substrate in an image input device, a wiring board 15 where a wiring layer is formed, a CCD 16 which photodetects an image inputted from outside through a lens and coverts it into an electric signal, a CCD driving circuit which drives the CCD 16, a display element driving circuit which drives a display element, and various semiconductor chips 17 where digital electric circuits including a recording device and a processor circuit, etc., are formed are mounted. In the above constitution, the CCD 16 and semiconductor chip 17 are fixed onto the same substrate 15 with an adhesive. Further, the CCD 16, bonding pads formed on the semiconductor chips 17, and a wiring layer formed on the wiring board 15 are connected by metal thin wires such as gold wires.

    CUBIC SYSTEM NITRIDE SEMICONDUCTOR DEVICE AND MANUFACTURE THEREOF
    9.
    发明专利
    CUBIC SYSTEM NITRIDE SEMICONDUCTOR DEVICE AND MANUFACTURE THEREOF 失效

    公开(公告)号：JPH1154438A

    公开(公告)日：1999-02-26

    申请号：JP20567397

    申请日：1997-07-31

    Applicant: MATSUSHITA ELECTRONICS CORP

    Inventor： YURI MASAAKI ,  UEDA TETSUZO ,  BABA TAKAAKI

    IPC: H01L29/20 ,  C30B25/02 ,  H01L21/20 ,  H01L21/203 ,  H01L21/205 ,  H01L33/32 ,  H01L33/00

    Abstract: PROBLEM TO BE SOLVED: To form a cubic-system nitride semiconductor layer of good crystallinity on a substrate, by nitriding one surface of a cubic-system semiconductor layer comprising aluminum, and forming a cubic-system nitride semiconductor layer on the surface. SOLUTION: By heating a substrate 1, in a molecular beam epitaxy device, and a irradiation with As molecular beam, an oxide present on the surface of the substrate 1 is removed. Then, by supplying Ga and Al, a semiconductor layer 2 of AlGaAs is formed. Then, irradiation with dimethylhydrazine is started to begin surface-nitriding of the semiconductor layer 2, and RED pattern representing a crystal state on the surface of a semiconductor layer 2 is monitored with a reflective high-speed electron diffraction device (RHEED), and when the RED pattern representing presence of AlGaAs changes to that representing presence of AlGaN, Ga is supplied in addition to the dimethylhydrazine, for growth of a cubic-system nitride semiconductor layer 3 constituted of GaN.

    SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
    10.
    发明专利
    SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF 失效

    公开(公告)号：JPH10163114A

    公开(公告)日：1998-06-19

    申请号：JP31910296

    申请日：1996-11-29

    Applicant: MATSUSHITA ELECTRONICS CORP

    Inventor： YURI MASAAKI ,  UEDA TETSUZO ,  BABA TAKAAKI

    IPC: H01L29/12 ,  H01L21/20 ,  H01L21/203 ,  H01L21/205 ,  H01S5/323

    Abstract: PROBLEM TO BE SOLVED: To homogenize a lead oxide layer and improve the reproducibility, by forming this lead oxide layer on a single crystal substrate, a first GaN crystal within specified temp. range and a second GaN crystal within specified temp. range. SOLUTION: Using a sputtering apparatus, a lead oxide layer 2 is formed on a sapphire-made single crystal substrate 1, and GaN target is sputtered in a substrate temp. range of O to 900 deg.C in an N atmosphere to form a first GaN crystal 4 which is them heated at 900-2000 deg.C in an ammonia atmosphere to form a second GaN crystal 5. Thus it is possible to homogenize the lead oxide layer 5 and form a p-n junction diode at a good reproducibility over the entire surface of the lead oxide layer 2.

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