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    11.
    发明专利
    未知

    公开(公告)号：DE69126618T2

    公开(公告)日：1998-01-08

    申请号：DE69126618

    申请日：1991-11-25

    Applicant: SGS THOMSON MICROELECTRONICS ,  CONS RIC MICROELETTRONICA

    Inventor： PAPARO MARIO ,  AIELLO NATALE

    IPC: H01L21/761 ,  H01L21/8222 ,  H01L27/06 ,  H01L27/082 ,  H02J1/00 ,  H01L21/76

    Abstract: The device consists of a bridge having at least two arms (1, 2) each formed of a first and a second diode-connected transistor (T11, T12; T21, T22). In the integrated monolithic embodiment each arm is formed by a type N+ substrate (3) connected to a positive potential output terminal (K1), type N- and N epitaxial layers (4, 19), type P, P+ regions (5,45; 6,46) contained within the epitaxial layers (4, 19) and containing within them a type N region (7; 8) which in turn contains a type P region (9; 10) connected to a negative potential output terminal (A1). Between the type P, P+ regions (5, 45; 6, 46) belonging to the first and the second arm (1, 2) there are first type N++ regions (11; 12) capable of minimising the current gain of the parasitic transistors (TP1a, TP1b) placed between the type P, P+ regions (5, 45; 6, 46) and second regions (13, 14) of type P and P+ respectively recovering the residual loss currents of the parasitic transistors (TP1a, TP1b).

    12.
    发明专利
    未知

    公开(公告)号：DE69126618D1

    公开(公告)日：1997-07-24

    申请号：DE69126618

    申请日：1991-11-25

    Applicant: SGS THOMSON MICROELECTRONICS ,  CONS RIC MICROELETTRONICA

    Inventor： PAPARO MARIO ,  AIELLO NATALE

    IPC: H01L21/761 ,  H01L21/8222 ,  H01L27/06 ,  H01L27/082 ,  H02J1/00 ,  H01L21/76

    Abstract: The device consists of a bridge having at least two arms (1, 2) each formed of a first and a second diode-connected transistor (T11, T12; T21, T22). In the integrated monolithic embodiment each arm is formed by a type N+ substrate (3) connected to a positive potential output terminal (K1), type N- and N epitaxial layers (4, 19), type P, P+ regions (5,45; 6,46) contained within the epitaxial layers (4, 19) and containing within them a type N region (7; 8) which in turn contains a type P region (9; 10) connected to a negative potential output terminal (A1). Between the type P, P+ regions (5, 45; 6, 46) belonging to the first and the second arm (1, 2) there are first type N++ regions (11; 12) capable of minimising the current gain of the parasitic transistors (TP1a, TP1b) placed between the type P, P+ regions (5, 45; 6, 46) and second regions (13, 14) of type P and P+ respectively recovering the residual loss currents of the parasitic transistors (TP1a, TP1b).

    14.
    发明专利
    未知

    公开(公告)号：IT1252623B

    公开(公告)日：1995-06-19

    申请号：ITMI913265

    申请日：1991-12-05

    Applicant: SGS THOMSON MICROELECTRONICS ,  CONS RIC MICROELETTRONICA

    Inventor： PAPARO MARIO ,  ZAMBRANO RAFFAELE

    IPC: H01L29/78 ,  H01L21/76 ,  H01L27/02 ,  H01L27/04 ,  H01L27/06 ,  H01L27/08 ,  H01L27/088 ,  H01L

    Abstract: In the device there are present a first, second and third switch designed to connect a node of the insulation region with a ground node, the collector or drain of the power transistor and a region of a control circuit transistor respectively. The dynamic insulation circuit of the control circuit comprises a pilot circuit which controls: closing of the first switch when the potential of the ground node (or insulation region) is less than the potential of the collector or drain region of the power transistor and the potential of the control circuit region, closing of the second switch and opening of the first when the potential of the collector or drain region of the power transistor is less than the potential of the ground node (or the insulation region), closing of the third switch and opening of the first when the potential of said control circuit region is less than the potential of the ground node (or the insulation region).

    15.
    发明专利
    未知

    公开(公告)号：IT1246759B

    公开(公告)日：1994-11-26

    申请号：IT2257790

    申请日：1990-12-31

    Applicant: SGS THOMSON MICROELECTRONICS ,  CONS RIC MICROELETTRONICA

    Inventor： PUZZOLO SANTO ,  ZAMBRANO RAFFAELE ,  PAPARO MARIO

    IPC: H01L21/8249 ,  H01L21/331 ,  H01L21/8222 ,  H01L27/06 ,  H01L27/082 ,  H01L29/73 ,  H01L29/732 ,  H01L

    Abstract: In the version with unisolated components the components of the structure are totally or partially superimposed on each other, partly in a first epitaxial layer and partly in a second epitaxial layer; the low voltage bipolar transistor is indeed situated above the emitter region of the bipolar power transistor which is thus a completely buried active structure. In the version with isolated components, in an n- epitaxial layer there are two p+ regions, i.e. the first, constituting the power transistor base, encloses the n+ emitter region of said transistor while the second encloses two n+ regions and one p+ region constituting the collector, emitter and base regions respectively of the low voltage transistor. A metallization on the front of the chip provides connection between the collector contact of the low voltage transistor and the emitter contact of the power transistor.

    LARGE-CURRENT MOS TRANSISTOR INTEGRATED BRIDGE STRUCTURE FOR OPTIMIZATION OF CONTINUITY POWER LOSS
    18.
    发明专利
    LARGE-CURRENT MOS TRANSISTOR INTEGRATED BRIDGE STRUCTURE FOR OPTIMIZATION OF CONTINUITY POWER LOSS 失效

    公开(公告)号：JPH05226597A

    公开(公告)日：1993-09-03

    申请号：JP31502492

    申请日：1992-11-25

    Applicant: ST MICROELECTRONICS SRL ,  CONS RIC MICROELETTRONICA

    Inventor： PAPARO MARIO ,  AIELLO NATALE

    IPC: H01L21/8238 ,  H01L21/761 ,  H01L27/088 ,  H01L27/092 ,  H01L29/78 ,  H02M7/219

    Abstract: PURPOSE: To provide a large-current MOS transistor integrated bridge which is formed in a monolithic structure on a single Si substrate, optimizing a conduction power loss. CONSTITUTION: An N -type substrate 3, which includes at least two arms respectively comprised of first and second MOS Trs and which forms a positive potential output terminal K1, covered with an N -type epitaxial layer 4. A bridge is comprised of a P and P -type insulating regions 13, 25 and 14, 16, including N -type drain regions 15, 16, N-type drain regions 19, 20 and a pair of N -type source regions 23, 24 forming continuously P-type main body regions 21, 22 and a negative potential output terminal with respect to each of the first Tr. The bridge also consists of an N -type drain regions 5, 6, including N-type drain regions 31, 32 with respect to each of the second Tr, continuously P-type main body regions 9, 10 and a pair of N -type regions 11, 12 forming respectively corresponding ac inputs A3, A4.

    19.
    发明专利
    失效

    公开(公告)号：JPH05252006A

    公开(公告)日：1993-09-28

    申请号：JP19823192

    申请日：1992-07-24

    Applicant: CONS RIC MICROELETTRONICA ,  ST MICROELECTRONICS SRL

    Inventor： ZISA MICHELE ,  BELLUSO MASSIMILIANO ,  PAPARO MARIO

    IPC: H03F3/217 ,  H03K4/58 ,  H03K5/02 ,  H03K17/06 ,  H03K17/687 ,  H03K19/017

    Abstract: PURPOSE: To actualize the bootstrap circuit which drives a power MOS transistor(TR) with high-potential side constitution wherein the power MOS TR is able to operate with a low-level supply voltage when operating at a high switching frequency. CONSTITUTION: The bootstrap circuit for the power MOS TR of the high- potential side driving constitution includes a 1st capacitor C1 which can be charged to a 1st voltage level of the supply voltage of the power TR T1. A 2nd capacitor C2 is provided in combination with the 1st capacitor C1 so that a 1st voltage and a 2nd voltage higher than the threshold voltage of the power TR T1 can be used.

    20.
    发明专利
    未知

    公开(公告)号：DE69128936T2

    公开(公告)日：1998-07-16

    申请号：DE69128936

    申请日：1991-11-25

    Applicant: ST MICROELECTRONICS SRL ,  CONS RIC MICROELETTRONICA

    Inventor： PAPARO MARIO ,  AIELLO NATALE

    IPC: H01L21/8238 ,  H01L21/761 ,  H01L27/088 ,  H01L27/092 ,  H01L29/78 ,  H02M7/219 ,  H01L21/76

    Abstract: The structure comprises at least arms (1, 2) each formed from a first and a second MOS transistor (M3, M1; M4, M2). Its integrated monolithic construction provides for a type N++ substrate (3) forming a positive potential output terminal (K1) which is overlaid by a type N-epitaxial layer (4). For each of the first transistors (M3; M4) this comprises a type P, P+ insulating region (13, 25; 14, 26) containing a type N+ enriched drain region (15; 16), a type N drain region (19; 20) and, in succession, a type P body region (21; 22) and a pair of type N+ source regions (23; 24) forming a negative potential output terminal (A1) respectively. For each of the second transistors (M1, M2) the structure comprises a type N+ enriched drain region (5, 6) containing a type N drain region (31, 32) and in succession a type P body region (9; 10) and a pair of type N+ regions (11; 12) forming corresponding alternating current inputs (A3, A4) respectively.

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