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    TERMINAL PART OF POWER STAGE OF MONOLITHIC SEMICONDUCTOR DEVICE AND RELATED MANUFACTURING PROCESS
    1.
    发明专利
    TERMINAL PART OF POWER STAGE OF MONOLITHIC SEMICONDUCTOR DEVICE AND RELATED MANUFACTURING PROCESS 失效

    公开(公告)号：JPH0653510A

    公开(公告)日：1994-02-25

    申请号：JP15092991

    申请日：1991-05-28

    Applicant: SGS THOMSON MICROELECTRONICS ,  CONS RIC MICROELETTRONICA

    Inventor： ZAMBRANO RAFFAELE ,  GRIMALDI ANTONIO

    IPC: H01L21/8249 ,  H01L21/76 ,  H01L27/06 ,  H01L27/088 ,  H01L29/78 ,  H01L29/784

    Abstract: PURPOSE: To maximize the breakdown voltage, without compromising the series resistance of a power stage and reliability of the device by making the min. distance of a structure junction from an embedded drain region shorter than or equal to that of this region from the junction of the peripheral region. CONSTITUTION: In a possible embodiment for the terminal of a power stage, a min. distance d1 between an embedded drain region 6 and this insulation region 9 is made smaller than that d2 between the buried drain region 9 from a junction 10, lying between a substrate and drain. In creating a device region 15, a substrate-drain junction 10 of an MOS power transistor must be connected to the region 9, as described above. The terminal length given from the region 9 is equal to the sum of the side face diffusions of the insulation regions, its photo-masked opening and error layout allowance. Its structure can maximize the operating voltage, without changing the series resistance of the power stage.

    SEMICONDUCTOR ELECTRONIC DEVICE PROVIDED WITH DYNAMIC INSULATION CIRCUIT
    2.
    发明专利
    SEMICONDUCTOR ELECTRONIC DEVICE PROVIDED WITH DYNAMIC INSULATION CIRCUIT 失效

    公开(公告)号：JPH06132538A

    公开(公告)日：1994-05-13

    申请号：JP32551992

    申请日：1992-12-04

    Applicant: SGS THOMSON MICROELECTRONICS ,  CONS RIC MICROELETTRONICA

    Inventor： PAPARO MARIO ,  ZAMBRANO RAFFAELE

    IPC: H01L29/78 ,  H01L21/76 ,  H01L27/02 ,  H01L27/04 ,  H01L27/06 ,  H01L27/08 ,  H01L27/088 ,  H01L29/784

    Abstract: PURPOSE: To allow a dynamic insulating circuit-equipped control circuit of a semiconductor electronic device to reliably keep the semiconductor electronic device insulated even in a negatively charged transient state. CONSTITUTION: A switch S1 connects an insulating region to a ground. A switch S2 connects the insulating region to a collector or drain of a power transistor. A switch S3 connects the insulating region to a control circuit transistor region. A dynamic insulating circuit of a control circuit is constructed of a driving circuit CPI. Such dynamic insulating circuit closes the switch S1 when the potential of the ground or insulating region is lower than the voltage of the collector or drain of the power transistor or the potential of the control circuit region, closes the switch S2 and opens the switch S1 simultaneously when the voltage of the collector or drain of the power transistor is lower than the potential of the ground or insulating region, and closes the switch S3 and opens the switch S1 simultaneously when the potential of the control circuit region is lower than the potential of the ground or insulating region.

    4.
    发明专利
    未知

    公开(公告)号：DE69122598T2

    公开(公告)日：1997-03-06

    申请号：DE69122598

    申请日：1991-12-18

    Applicant: SGS THOMSON MICROELECTRONICS ,  CONS RIC MICROELETTRONICA

    Inventor： PUZZOLO SANTO ,  ZAMBRANO RAFFAELE ,  PAPARO MARIO

    IPC: H01L21/8249 ,  H01L21/331 ,  H01L21/8222 ,  H01L27/06 ,  H01L27/082 ,  H01L29/73 ,  H01L29/732 ,  H01L21/82

    Abstract: In the version with unisolated components the components of the structure are totally or partially superimposed on each other, partly in a first epitaxial layer and partly in a second epitaxial layer; the low voltage bipolar transistor is indeed situated above the emitter region of the bipolar power transistor which is thus a completely buried active structure. In the version with isolated components, in an n- epitaxial layer there are two p+ regions, i.e. the first, constituting the power transistor base, encloses the n+ emitter region of said transistor while the second encloses two n+ regions and one p+ region constituting the collector, emitter and base regions respectively of the low voltage transistor. A metallization on the front of the chip provides connection between the collector contact of the low voltage transistor and the emitter contact of the power transistor.

    7.
    发明专利
    未知

    公开(公告)号：DE69029942T2

    公开(公告)日：1997-08-28

    申请号：DE69029942

    申请日：1990-10-16

    Applicant: SGS THOMSON MICROELECTRONICS ,  CONS RIC MICROELETTRONICA

    Inventor： ZAMBRANO RAFFAELE ,  MAGRO CARMELO

    IPC: H01L21/336 ,  H01L29/10 ,  H01L29/78 ,  H01L29/772

    Abstract: The process provides first for the accomplishment of low-doping body regions (12) at the sides and under a gate region (15) and then the accomplishment of high-doping body regions (14) inside said low-doping body regions (12) and self-aligned with said gate region (15). There is thus obtained an MOS power transistor with vertical current flow which has high-doping body regions (14) self-aligned with said gate region (15) and with a reduced junction depth.

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