公开(公告)号：WO2004055895A1

公开(公告)日：2004-07-01

申请号：PCT/US2003/039537

申请日：2003-12-12

Applicant: FORMFACTOR, INC.

Inventor： KHANDROS, Igor, K. ,  ELDRIDGE, Benjamin, N. ,  MILLER, Charles, A. ,  SPORCK, A., Nicholas ,  GRUBE, Gary, W. ,  MATHIEU, Gaetan, L.

IPC: H01L25/065

CPC classification number: H01L23/13 ,  H01L23/4951 ,  H01L23/5386 ,  H01L23/5387 ,  H01L24/48 ,  H01L24/49 ,  H01L24/50 ,  H01L25/0655 ,  H01L2224/0401 ,  H01L2224/05554 ,  H01L2224/06136 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48139 ,  H01L2224/4824 ,  H01L2224/49 ,  H01L2224/73215 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01006 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/0105 ,  H01L2924/014 ,  H01L2924/10161 ,  H01L2924/14 ,  H01L2924/15192 ,  H01L2924/181 ,  H01L2924/19043 ,  H01L2924/19107 ,  H01L2924/3011 ,  H01L2924/3025 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/05599 ,  H01L2924/00

Abstract: In an integrated circuit assembly, know good die (KGD) are assembled on a substrate. Interconnect elements electrically connect pads on a die attached to the substrate to traces or other electrical conductors on the substrate or to pads on another die attached to the substrate. The substrate may have one or more openings, exposing pads of the die. The assembly may comprise one or more dice.

Abstract translation: 在集成电路组件中，将好的芯片（KGD）组装在基板上。 互连元件将附接到衬底的芯片上的焊盘电连接到衬底上的迹线或其它电导体或连接到衬底的另一芯片上的焊盘。 衬底可以具有一个或多个开口，暴露管芯的焊盘。 组件可以包括一个或多个骰子。

公开(公告)号：WO2004053976A2

公开(公告)日：2004-06-24

申请号：PCT/US2003/038463

申请日：2003-12-02

Applicant: FORMFACTOR, INC.

Inventor： KHANDROS, Igor, K. ,  MATHIEU, Gaetan, L. ,  REYNOLDS, Carl, V.

IPC: H01L21/66

CPC classification number: G01R3/00 ,  G01R1/0433 ,  G01R1/0483 ,  G01R1/07378 ,  G01R31/2863 ,  H01L24/13 ,  H01L2224/131 ,  H01L2924/01046 ,  H01L2924/01055 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/14 ,  Y10T29/49117 ,  Y10T29/4913 ,  Y10T29/49144 ,  Y10T29/49149 ,  Y10T29/49169 ,  Y10T29/49179 ,  Y10T29/49197 ,  Y10T29/49204 ,  Y10T29/4921 ,  Y10T29/49211 ,  Y10T29/49224 ,  Y10T29/53217 ,  Y10T29/53265 ,  H01L2924/014

Abstract: A interconnect structure is inexpensively manufactured and easily insertable into a socket. The interconnect structure is manufactured by forming a sacrificial substrate with cavities that is covered by a masking material having openings corresponding to the cavities. A first plating process is performed by depositing conductive material, followed by coupling wires within the openings and performing another plating process by depositing more conductive material. The interconnect structure is completed by first removing the masking material and sacrificial substrate. Ends of the wires are coupled opposite now-formed contact structures to a board. To complete the socket, a support device is coupled to the board to hold a tested integrated circuit.

Abstract translation: 互连结构便宜地制造并且可以容易地插入到插座中。 互连结构通过形成具有空腔的牺牲基板来制造，所述空腔被具有对应于空腔的开口的掩模材料覆盖。 通过沉积导电材料，随后在开口内耦合导线并通过沉积更多导电材料来执行另一电镀工艺来执行第一电镀工艺。 通过首先去除掩模材料和牺牲衬底来完成互连结构。 电线的端部与现在形成的接触结构相对地耦合到电路板。 为了完成插座，支撑装置连接到电路板以保持经测试的集成电路。

公开(公告)号：EP1407280B1

公开(公告)日：2005-11-23

申请号：EP02742417.5

申请日：2002-07-10

Applicant: FormFactor, Inc.

Inventor： GRUBE, Gary, W. ,  KHANDROS, Igor, K. ,  ELDRIDGE, Benjamin, N. ,  MATHIEU, Gaetan, L. ,  LOTFIZADEH, Poya ,  TSENG, Chih-Chiang

IPC: G01R1/073

CPC classification number: G01R31/2886 ,  G01R1/07314 ,  G01R1/07342 ,  G01R1/07357 ,  G01R1/07378 ,  G01R3/00 ,  Y10T29/49126

Abstract: A method of designing and manufacturing a probe card assembly includes prefabricating one or more elements of the probe card assembly to one or more predefined designs. Thereafter, design data regarding a newly designed semiconductor device is received along with data describing the tester and testing algorithms to be used to test the semiconductor device. Using the received data, one or more of the prefabricated elements is selected. Again using the received data, one or more of the selected prefabricated elements is customized. The probe card assembly is then built using the selected and customized elements.

公开(公告)号：EP1468048A1

公开(公告)日：2004-10-20

申请号：EP03703894.0

申请日：2003-01-16

Applicant: FORMFACTOR, INC.

Inventor： KHANDROS, Igor, K. ,  ELDRIDGE, Benjamin, N. ,  FANG, Treliant ,  MATHIEU, Gaetan, L. ,  GRUBE, Gary, W. ,  DRUSH, Michael, A. ,  BUCKHOLTZ, Christopher, C.

IPC: C08L83/04 ,  C08G77/06 ,  G01R31/02 ,  B08B1/00

CPC classification number: C08G77/48 ,  B08B1/00 ,  B08B7/0028 ,  G01R1/06711 ,  G01R3/00 ,  Y10T428/24388 ,  Y10T428/31663

Abstract: A probe cleaning apparatus for cleaning a probe tip use to test semiconductors dies having an abrasive substrate layer an a tacky gel layer on top of the abrasive surface of the abrasive substrate layer. The probe tip is cleaned by passing it through the tacky gel layer so that it comes in contact with the abrasive surface of the abrasive substrate, moving the probe tip across the abrasive surface of the substrate layer, and then removing the probe tip from the successive layers of the cleaning apparatus. The probe tip emerges from the cleaning apparatus free from debris associated with testing the semiconductor dies.

公开(公告)号：EP1570277B1

公开(公告)日：2010-02-10

申请号：EP03796616.5

申请日：2003-12-02

Applicant: FormFactor, Inc.

Inventor： KHANDROS, Igor, K. ,  MATHIEU, Gaetan, L. ,  REYNOLDS, Carl, V.

IPC: G01R1/073

CPC classification number: G01R3/00 ,  G01R1/0433 ,  G01R1/0483 ,  G01R1/07378 ,  G01R31/2863 ,  H01L24/13 ,  H01L2224/131 ,  H01L2924/01046 ,  H01L2924/01055 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/14 ,  Y10T29/49117 ,  Y10T29/4913 ,  Y10T29/49144 ,  Y10T29/49149 ,  Y10T29/49169 ,  Y10T29/49179 ,  Y10T29/49197 ,  Y10T29/49204 ,  Y10T29/4921 ,  Y10T29/49211 ,  Y10T29/49224 ,  Y10T29/53217 ,  Y10T29/53265 ,  H01L2924/014

公开(公告)号：EP1690283A2

公开(公告)日：2006-08-16

申请号：EP04812006.7

申请日：2004-11-22

Applicant: FormFactor, Inc.

Inventor： MATHIEU, Gaetan, L. ,  KHANDROS, Igor, K. ,  REYNOLDS, Carl, V.

IPC: H01K3/10

CPC classification number: H05K3/42 ,  G01R1/06711 ,  G01R1/07307 ,  G01R3/00 ,  H05K3/308 ,  H05K2201/09836 ,  H05K2203/0338

Abstract: Methods are provide for making vertical feed through electrical connections structure in a substrate or tile. The vertical feed through (Fig. 2, 10) can be configured to make plated through holes usable for inserting and attaching connector probes ( Fig. 2, 12). Probes may be attached to the plated through holes or attachment wells to create resilient spring contacts to form a wafer probe card assembly. A twisted tube plated through hole structure (Fig. 9D, 74) is formed by supporting twisted sacrificial wire coated with the plating material in a substrate (Fig. 9D, 79), and later etching away the wires (Fig. 9A, 74).

公开(公告)号：EP1570277A2

公开(公告)日：2005-09-07

申请号：EP03796616.5

申请日：2003-12-02

Applicant: FormFactor, Inc.

Inventor： KHANDROS, Igor, K. ,  MATHIEU, Gaetan, L. ,  REYNOLDS, Carl, V.

IPC: G01R1/073

CPC classification number: G01R3/00 ,  G01R1/0433 ,  G01R1/0483 ,  G01R1/07378 ,  G01R31/2863 ,  H01L24/13 ,  H01L2224/131 ,  H01L2924/01046 ,  H01L2924/01055 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/14 ,  Y10T29/49117 ,  Y10T29/4913 ,  Y10T29/49144 ,  Y10T29/49149 ,  Y10T29/49169 ,  Y10T29/49179 ,  Y10T29/49197 ,  Y10T29/49204 ,  Y10T29/4921 ,  Y10T29/49211 ,  Y10T29/49224 ,  Y10T29/53217 ,  Y10T29/53265 ,  H01L2924/014

Abstract: A interconnect structure is inexpensively manufactured and easily insertable into a socket. The interconnect structure is manufactured by forming a sacrificial substrate with cavities that is covered by a masking material having openings corresponding to the cavities. A first plating process is performed by depositing conductive material, followed by coupling wires within the openings and performing another plating process by depositing more conductive material. The interconnect structure is completed by first removing the masking material and sacrificial substrate. Ends of the wires are coupled opposite now-formed contact structures to a board. To complete the socket, a support device is coupled to the board to hold a tested integrated circuit.

公开(公告)号：EP2059977A2

公开(公告)日：2009-05-20

申请号：EP07814273.4

申请日：2007-08-21

Applicant: FormFactor, Inc.

Inventor： ELDRIDGE, Benjamin, N. ,  GRITTERS, John K. ,  KHANDROS, Igor, K. ,  MARTENS, Rod ,  MATHIEU, Gaetan, L.

IPC: H01R12/00

CPC classification number: G01R1/06755 ,  H01R13/03 ,  Y10T29/49204

Abstract: A carbon nanotube contact structure (1400) can be used for making pressure connections to a DUT The contact structure can be formed using a carbon nanotube film (1100) or with carbon nanotubes in solution The carbon nanotube film can be grown in a trench in a sacrificial substrate in which a contact structure such as a beam or contact element (1403) is then formed by metal plating The film can also be formed on a contact element and have metal posts dispersed therein to provide rigidity and elasticity Contact structures or portions thereof can also be plated with a solution containing carbon nanotubes The resulting contact structure can be tough, and can provide good electrical conductivity.

公开(公告)号：EP1716422A1

公开(公告)日：2006-11-02

申请号：EP05723223.3

申请日：2005-02-15

Applicant: FormFactor, Inc.

Inventor： COOPER, Timothy, E. ,  ELDRIDGE, Benjamin, N. ,  KHANDROS, Igor, K. ,  MARTENS, Rod ,  MATHIEU, Gaetan, L.

IPC: G01R31/02

CPC classification number: G01R31/2886 ,  G01R31/2887

Abstract: An electronic device is moved into a first position such that terminals of the electronic device are adjacent probes for making electrical contact with the terminals. The electronic device is then moved horizontally or diagonally such that the terminals contact the probes. Test data are then communicated to and from the electronic device through the probes.

公开(公告)号：EP1616353A2

公开(公告)日：2006-01-18

申请号：EP04759413.0

申请日：2004-04-12

Applicant: FormFactor, Inc.

Inventor： KHANDROS, Igor, K. ,  MILLER, Charles, A. ,  WENZEL, Stuart, W.

IPC: H01L23/485 ,  H01L23/48

CPC classification number: H05K3/4007 ,  H01L24/13 ,  H01L24/72 ,  H01L24/81 ,  H01L2224/05001 ,  H01L2224/05027 ,  H01L2224/05548 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2224/73251 ,  H01L2224/81901 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01022 ,  H01L2924/01027 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01058 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/3011 ,  H01L2924/3025 ,  H01L2924/351 ,  H01R12/57 ,  H01R43/007 ,  H05K3/326 ,  H05K2201/0133 ,  H05K2201/0367 ,  H05K2201/09909 ,  Y10T29/49147 ,  H01L2924/00 ,  H01L2224/16 ,  H01L2224/72 ,  H01L2224/05599 ,  H01L2224/05099

Abstract: A microelectronic spring contact for making electrical contact between a device and a mating substrate and method of making the same are disclosed. The spring contact has a compliant pad adhered to a substrate of the device and spaced apart from a terminal of the device. The compliant pad has a base adhered to the substrate, and side surfaces extending away from the substrate and tapering to a smaller end area distal from the substrate. A trace extends from the terminal of the device over the compliant pad to its end area. At least a portion of the compliant pad end area is covered by the trace, and a portion of the trace that is over the compliant pad is supported by the compliant pad.