公开(公告)号：WO2004055868A3

公开(公告)日：2004-10-07

申请号：PCT/US0339594

申请日：2003-12-10

Applicant: HRL LAB LLC ,  CHOW LAP-WAI ,  CLARK WILLIAM M JR ,  BAUKUS JAMES P ,  HARBISON GAVIN J

Inventor： CHOW LAP-WAI ,  CLARK WILLIAM M JR ,  BAUKUS JAMES P ,  HARBISON GAVIN J

IPC: H01L21/8238 ,  H01L27/02 ,  H01L29/76

CPC classification number: H01L21/823892 ,  H01L27/02

Abstract: A technique for and structures for camouflaging an integrated circuit structure. The integrated circuit structure is formed having a well of a first conductivity type under the gate region being disposed adjacent to active regions of a first conductivity type. The well forming an electrical path between the active regions regardless of any reasonable voltage applied to the integrated circuit structure.

Abstract translation: 用于伪装集成电路结构的技术和结构。 集成电路结构形成为具有第一导电类型的阱，栅极区域邻近第一导电类型的有源区设置。 该阱在有源区域之间形成电路径，而不管施加到集成电路结构的任何合理的电压。

公开(公告)号：WO02059964A3

公开(公告)日：2003-01-23

申请号：PCT/US0202261

申请日：2002-01-24

Applicant: HRL LAB LLC ,  CHOW LAP-WAI ,  BAUKUS JAMES P ,  CLARK WILLIAM M JR

Inventor： CHOW LAP-WAI ,  BAUKUS JAMES P ,  CLARK WILLIAM M JR

IPC: H01L23/58 ,  H01L23/522

CPC classification number: H01L23/57 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Semiconducting devices, including integrated circuits, are protected from reverse engineering by passivation openings made in a passivation layer. When a reverse engineeretches away the passivation layer and typically the first metal layer, underlying metallayers and/or other elements of the device are destroyed making the reverse engineeringall the more difficult. A method for fabricating such devices is also disclosed.

Abstract translation: 包括集成电路在内的半导体器件通过在钝化层中形成的钝化开关得到保护，防止逆向工程化。 当反向引擎消除钝化层并且通常是第一金属层时，器件的下面的金属层和/或其它元件被破坏，从而使得反向工程更困难。 还公开了一种用于制造这种装置的方法。

公开(公告)号：GB2432971A

公开(公告)日：2007-06-06

申请号：GB0702704

申请日：2003-11-20

Applicant: HRL LAB LLC ,  RAYTHEON CO ,  CHOW LAP-WAI ,  CLARK WILLIAM M JR ,  HARBISON GAVIN J ,  BAUKUS JAMES P

Inventor： CHOW LAP-WAI ,  CLARK WILLIAM M JR ,  HARBISON GAVIN J ,  BAUKUS JAMES P

IPC: H01L27/02 ,  H01L23/58

Abstract: The similarity of non-operable and operable transistors in an integrated circuit is increased by ensuring that the distance between the gate and source or drain electrodes is the same for both types of transistor. The use of non-operable transistors allow the circuit designer to disguise an AND gate so that it appears to be an OR gate to the reverse engineer. The disguised non-operable transistors cause the circuitry to operate in an unexpected manner to the reverse engineer.

公开(公告)号：GB2422956B

公开(公告)日：2007-05-23

申请号：GB0608053

申请日：2003-11-20

Applicant: HRL LAB LLC ,  RAYTHEON CO

Inventor： CHOW LAP-WAI ,  CLARK WILLIAM M JR ,  HARBISON GAVIN J ,  BAUKUS JAMES P

IPC: H01L27/02 ,  H01L23/58

Abstract: A technique for and structures for camouflaging an integrated circuit structure. A layer of conductive material having a controlled outline is disposed to provide artifact edges of the conductive material that resemble an operable device when in fact the device is not operable.

公开(公告)号：GB2391986B

公开(公告)日：2005-08-10

申请号：GB0325521

申请日：2002-03-12

Applicant: HRL LAB LLC

Inventor： CLARK JR WILLIAM M ,  CHOW LAP-WAI ,  BAUKUS JAMES P

IPC: G11C17/18 ,  G06F12/14 ,  G11C7/12 ,  G11C7/18 ,  G11C7/24 ,  G11C16/02 ,  G11C16/22 ,  H01L21/8246 ,  H01L21/8247 ,  H01L27/02 ,  H01L27/10 ,  H01L27/112 ,  H01L27/115

Abstract: A method and circuit for blocking unauthorized access to at least one memory cell in a semiconductor memory. The method includes providing a switch and/or a link which assumes an open state when access to the at least one memory cell is to be blocked; and coupling-a data line associated with the at least one memory cell to a constant voltage source in response to the switch or link assuming an open state.

公开(公告)号：GB2405531A

公开(公告)日：2005-03-02

申请号：GB0427115

申请日：2003-05-06

Applicant: HRL LAB LLC ,  RAYTHEON CO

Inventor： CHOW LAP-WAI ,  CLARK JR WILLIAM M ,  BAUKUS JAMES P

IPC: H01L21/331 ,  H01L21/822 ,  H01L21/8238 ,  H01L21/8247 ,  H01L23/58 ,  H01L27/02 ,  H01L27/04 ,  H01L27/092 ,  H01L27/115 ,  H01L29/732 ,  H01L29/78 ,  H01L29/788 ,  H01L29/792

Abstract: Technique and structures for camouflaging an integrated circuit structure. The integrated circuit structure is formed by a plurality of layers of material having controlled outlines and controlled thicknesses. A layer of dielectric material of a controlled thickness is disposed among said plurality of layers to thereby render the integrated circuit structure intentionally inoperable.

公开(公告)号：AU2003293540A1

公开(公告)日：2004-07-09

申请号：AU2003293540

申请日：2003-12-10

Applicant: HRL LAB LLC

Inventor： CHOW LAP-WAI ,  CLARK WILLIAM M JR ,  BAUKUS JAMES P ,  HARBISON GAVIN J

IPC: H01L21/8238 ,  H01L27/02 ,  H01L29/76

Abstract: A technique for and structures for camouflaging an integrated circuit structure. The integrated circuit structure is formed having a well of a first conductivity type under the gate region being disposed adjacent to active regions of a first conductivity type. The well forming an electrical path between the active regions regardless of any reasonable voltage applied to the integrated circuit structure.

公开(公告)号：DE10196819T5

公开(公告)日：2004-04-15

申请号：DE10196819

申请日：2001-05-11

Applicant: HRL LAB LLC

Inventor： CLARK JUN WILLIAM M ,  BAUKUS JAMES P ,  CHOW LAP-WAI

IPC: H01L27/04 ,  H01L21/74 ,  H01L21/822 ,  H01L21/8234 ,  H01L27/02 ,  H01L27/088 ,  H01L21/768

公开(公告)号：AU2003245265A1

公开(公告)日：2003-12-02

申请号：AU2003245265

申请日：2003-05-06

Applicant: HRL LAB LLC

Inventor： CLARK JR WILLIAM M ,  BAUKUS JAMES P ,  CHOW LAP-WAI

IPC: H01L21/331 ,  H01L21/822 ,  H01L21/8238 ,  H01L21/8247 ,  H01L23/58 ,  H01L27/02 ,  H01L27/04 ,  H01L27/092 ,  H01L27/115 ,  H01L29/732 ,  H01L29/78 ,  H01L29/788 ,  H01L29/792

公开(公告)号：AU6141801A

公开(公告)日：2002-05-06

申请号：AU6141801

申请日：2001-05-11

Applicant: HRL LAB LLC

Inventor： CLARK WILLIAM M JR ,  BAUKUS JAMES P ,  CHOW LAP-WAI

IPC: H01L27/04 ,  H01L21/74 ,  H01L21/822 ,  H01L21/8234 ,  H01L27/02 ,  H01L27/088 ,  H01L21/768