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    METHOD OF FORMING RELAXED SiGe LAYER
    11.
    发明专利
    METHOD OF FORMING RELAXED SiGe LAYER 审中-公开
    形成松散SiGe层的方法

    公开(公告)号：JP2006032962A

    公开(公告)日：2006-02-02

    申请号：JP2005204182

    申请日：2005-07-13

    Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

    Inventor： BEDELL STEPHEN W ,  CHEN HUAJIE ,  FOGEL KEITH E ,  SADANA DEVENDRA K ,  SHAHIDI GHAVAM G

    IPC: H01L21/20

    CPC classification number: H01L21/26506 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/02694

    Abstract: PROBLEM TO BE SOLVED: To provide a method for suppressing the formation of flat surface defects, such as stacking faults and microtwins in a relaxed SiGe alloy layer.
    SOLUTION: There is disclosed the method of manufacturing a substantially-relaxed SiGe alloy layer, in which flat surface defect density is decreased. The method comprises the steps of forming a strained Ge-containing layer on the front surface of an Si-containing substrate, implanting ions into the interface of the Ge-containing layer/the Si-containing substrate or under the interface, and forming the substantially-relaxed SiGe alloy layer, in which the flat surface defect density is decreased. Further, there are also provided a substantially relaxed SiGe-on-insulator, having an SiGe layer in which the flat surface defect density is decreased, and a heterostructure comprising the insulator.
    COPYRIGHT: (C)2006,JPO&NCIPI

    Abstract translation: 要解决的问题：提供一种抑制在弛豫SiGe合金层中形成平坦表面缺陷的方法，例如层叠缺陷和微丝。 解决方案：公开了制造基本上松弛的SiGe合金层的方法，其中平坦表面缺陷密度降低。 该方法包括以下步骤：在含Si衬底的前表面上形成应变的含锗层，将离子注入含Ge层/含Si衬底的界面或界面之下，并形成基本上 不透明的SiGe合金层，其中平坦表面缺陷密度降低。 此外，还提供了具有其中平坦表面缺陷密度降低的SiGe层和包含绝缘体的异质结构的基本上松弛的绝缘体上SiGe。 版权所有（C）2006，JPO＆NCIPI

    SINGLE-JUNCTION PHOTOVOLTAIC CELL
    14.
    发明申请
    SINGLE-JUNCTION PHOTOVOLTAIC CELL 审中-公开
    单晶光伏电池

    公开(公告)号：WO2011106204A2

    公开(公告)日：2011-09-01

    申请号：PCT/US2011024949

    申请日：2011-02-16

    Applicant: IBM ,  BEDELL STEPHEN W ,  FOGEL KEITH E ,  SOSA CORTES NORMA E ,  SADANA DEVENDRA ,  SHAHRJERDI DAVOOD ,  WACASER BRENT A

    Inventor： BEDELL STEPHEN W ,  FOGEL KEITH E ,  SOSA CORTES NORMA E ,  SADANA DEVENDRA ,  SHAHRJERDI DAVOOD ,  WACASER BRENT A

    IPC: H01L31/042 ,  H01L31/06

    CPC classification number: H01L31/0304 ,  H01L31/0725 ,  H01L31/074 ,  H01L31/075 ,  H01L31/076 ,  H01L31/184 ,  H01L31/1892 ,  Y02E10/548

    Abstract: A method for forming a single-junction photovoltaic cell includes forming a dopant layer on a surface of a semiconductor substrate; diffusing the dopant layer into the semiconductor substrate to form a doped layer of the semiconductor substrate; forming a metal layer over the doped layer, wherein a tensile stress in the metal layer is configured to cause a fracture in the semiconductor substrate; removing a semiconductor layer from the semiconductor substrate at the fracture; and forming the single-junction photovoltaic cell using the semiconductor layer. A single-junction photovoltaic cell includes a doped layer comprising a dopant diffused into a semiconductor substrate; a patterned conducting layer formed on the doped layer; a semiconductor layer comprising the semiconductor substrate located on the doped layer on a surface of the doped layer opposite the patterned conducting layer; and an ohmic contact layer formed on the semiconductor layer.

    Abstract translation: 一种形成单结光伏电池的方法包括在半导体衬底的表面上形成掺杂剂层; 将掺杂剂层扩散到半导体衬底中以形成半导体衬底的掺杂层; 在所述掺杂层上形成金属层，其中所述金属层中的拉伸应力构造成在所述半导体衬底中引起断裂; 在断裂时从半导体衬底去除半导体层; 以及使用半导体层形成单结光伏电池。 单结光伏电池包括掺杂剂，该掺杂层包含扩散到半导体衬底中的掺杂剂; 形成在掺杂层上的图案化导电层; 半导体层，其包括位于掺杂层的与图案化导电层相对的表面上的掺杂层上的半导体衬底; 以及形成在半导体层上的欧姆接触层。

    DUAL-GATE BIO/CHEM SENSOR
    15.
    发明申请
    DUAL-GATE BIO/CHEM SENSOR 审中-公开
    双门生物/ CHEM传感器

    公开(公告)号：WO2014062285A2

    公开(公告)日：2014-04-24

    申请号：PCT/US2013054601

    申请日：2013-08-13

    Applicant: IBM

    Inventor： BEDELL STEPHEN W ,  HEKMATSHOARTABARI BAHMAN ,  SHAHIDI GHAVAM G ,  SHAHRJERDI DAVOOD

    IPC: H01L21/336

    CPC classification number: H01L29/78648 ,  H01L21/84

    Abstract: A dual gate extremely thin semiconductor-on-insulator transistor with asymmetric gate dielectrics is provided. This structure can improve the sensor detection limit and also relieve the drift effects. Detection is performed at a constant current mode while the species will be detected at a gate electrode with a thin equivalent oxide thickness (EOT) and the gate bias will be applied to the second gate electrode with thicker EOT to maintain current flow through the transistor. As a result, a small change in the charge on the first electrode with the thin EOT will be translated into a larger voltage on the gate electrode with the thick EOT to sustain the current flow through the transistor. This allows a reduction of the sensor dimension and therefore an increase in the array size. The dual gate structure further includes cavities, i.e., microwell arrays, for chemical sensing.

    Abstract translation: 提供了具有非对称栅极电介质的双栅非常薄的绝缘体上半导体晶体管。 这种结构可以提高传感器的检测极限，也可以减轻漂移的影响。 以恒定电流模式进行检测，同时将在具有薄当量氧化物厚度（EOT）的栅电极处检测物种，并且将栅极偏压施加到具有较大EOT的第二栅电极，以保持电流流过晶体管。 结果，具有薄EOT的第一电极上的电荷的小的变化将被转换成具有较厚EOT的栅电极上的较大电压，以维持通过晶体管的电流。 这允许减小传感器尺寸并因此减小阵列尺寸。 双栅极结构还包括用于化学感测的空腔，即微孔阵列。

    Bipolar junction transistor, and method of forming same
    17.
    发明专利
    Bipolar junction transistor, and method of forming same 有权
    双极接头晶体管及其形成方法

    公开(公告)号：JP2007158333A

    公开(公告)日：2007-06-21

    申请号：JP2006322586

    申请日：2006-11-29

    Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

    Inventor： WALLNER THOMAS A ,  BEDELL STEPHEN W ,  THOMAS N ADAM ,  DE SOUZA JOEL P

    IPC: H01L21/331 ,  H01L21/76 ,  H01L21/8222 ,  H01L27/082 ,  H01L29/737

    CPC classification number: H01L29/732 ,  H01L29/0649 ,  H01L29/0657 ,  H01L29/1004 ,  H01L29/66242 ,  H01L29/66272 ,  H01L29/7378

    Abstract: PROBLEM TO BE SOLVED: To provide an improved bipolar junction transistor (BJT) characterized in that the parasitic capacitance has been reduced without reduction in base resistance accompanying the reduction in the parasitic capacitance, and to provide a method of forming the same.
    SOLUTION: The collector region of each BJT is arranged in the surface of a semiconductor substrate and adjacent to a first shallow trench isolation (STI) region. A second STI region is formed while the second STI region extends between the first STI region and the collector region, and undercuts a part of an active base region with an undercut angle of about 90° or less. For example, the second STI region may have a section with a substantially triangular shape with an undercut angle of less than about 90° or a section with a substantially rectangular shape with an undercut angle of about 90°. Such a second STI region can be manufactured using a porous surface part formed in the upper side surface of the collector region.
    COPYRIGHT: (C)2007,JPO&INPIT

    Abstract translation: 要解决的问题：提供一种改进的双极结型晶体管（BJT），其特征在于，随着寄生电容的减小，寄生电容已经降低而基极电阻没有降低，并且提供了其形成方法。 解决方案：每个BJT的集电极区域布置在半导体衬底的表面中并与第一浅沟槽隔离（STI）区域相邻。 形成第二STI区域，同时第二STI区域在第一STI区域和收集区域之间延伸，并且底切角为约90°或更小的一部分有源基区域。 例如，第二STI区域可以具有具有小于约90°的底切角的基本三角形形状的截面或具有约90°的底切角的基本矩形形状的截面。 可以使用形成在集电区域的上侧表面中的多孔表面部分来制造这样的第二STI区域。 版权所有（C）2007，JPO＆INPIT

    Method improving quality of defective semiconductor material
    18.
    发明专利
    Method improving quality of defective semiconductor material 有权
    改善缺陷半导体材料质量的方法

    公开(公告)号：JP2005094006A

    公开(公告)日：2005-04-07

    申请号：JP2004266302

    申请日：2004-09-14

    Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

    Inventor： BEDELL STEPHEN W ,  FOGEL KEITH E ,  NARASIMHA SHREESH

    IPC: H01L21/02 ,  H01L21/20 ,  H01L21/265 ,  H01L27/12

    CPC classification number: H01L21/2022 ,  Y10S438/933

    Abstract: PROBLEM TO BE SOLVED: To provide an improving method of the quality of a defective semiconductor crystal in the vicinity of the surface thereof.
    SOLUTION: A method where amorphization step and subsequent thermal treatment step are executed on the defective semiconductor crystal material is provided. In the amorphization step, a region including the surface area of the defective semiconductor crystal material is partially or completely amorphized. Next, the thermal treatment step is executed to recrystallize the amorphized area of the defective semiconductor crystal material. Recrystallization is achieved, by re-growing the solid phase crystal from the amorphized area of the defective semiconductor crystal material.
    COPYRIGHT: (C)2005,JPO&NCIPI

    Abstract translation: 要解决的问题：提供在其表面附近的缺陷半导体晶体的质量的改进方法。 解决方案：提供了对缺陷半导体晶体材料执行非晶化步骤和随后的热处理步骤的方法。 在非晶化步骤中，包含缺陷半导体晶体材料的表面积的区域部分或完全非晶化。 接下来，进行热处理步骤，使缺陷半导体晶体材料的非晶化区域重结晶。 通过从有缺陷的半导体晶体材料的非晶化区域重新生长固相晶体来实现重结晶。 版权所有（C）2005，JPO＆NCIPI

    Defect control by oxidation of silicon
    19.
    发明专利
    Defect control by oxidation of silicon 有权
    氧化硅缺陷控制

    公开(公告)号：JP2005026681A

    公开(公告)日：2005-01-27

    申请号：JP2004183839

    申请日：2004-06-22

    Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

    Inventor： BEDELL STEPHEN W ,  CHEN HUAJIE ,  DOMENICUCCI ANTHONY G ,  FOGEL KEITH E ,  SADANA DEVENDRA K

    IPC: H01L27/12 ,  H01L21/02 ,  H01L21/20 ,  H01L21/762

    CPC classification number: H01L21/7624 ,  Y10S438/933 ,  Y10T428/12674

    Abstract: PROBLEM TO BE SOLVED: To provide a method for manufacturing an SiGe-on-insulator substrate material substantially relaxed, of high quality, and capable of being used as a template for strained-silicon. SOLUTION: The SOI substrate having an ultra-thin top Si layer is used as the template for compressive strain SiGe growth. When an SiGe layer is relaxed at an enough temperature, the property of its dislocation movement is such that strain release defect moves down into the thin Si layer when an embedded oxide shows semi-viscosity behavior. The thin Si layer is consumed by oxidation of an interface of the thin Si with the embedded oxide. This can be performed by using inner oxidation at a high temperature. Therefore, the role of the original thin Si layer is to use the inner oxidation and subsequently to act as a sacrificial defective sink capable of being consumed during an SiGe alloy being relaxed. COPYRIGHT: (C)2005,JPO&NCIPI

    Abstract translation: 要解决的问题：提供一种制造绝缘体上绝缘体衬底材料的方法，其基本上是松弛的，高质量的，并且能够用作应变硅的模板。 解决方案：使用具有超薄顶部Si层的SOI衬底作为压缩应变SiGe生长的模板。 当SiGe层在足够的温度下松弛时，其位错运动的性质使得当嵌入的氧化物显示半粘度行为时，应变释放缺陷向下移动到薄的Si层中。 薄的Si层被薄的Si与嵌入的氧化物的界面的氧化所消耗。 这可以通过在高温下使用内部氧化来进行。 因此，原始薄Si层的作用是使用内部氧化，随后作为在SiGe合金松弛期间能够消耗的牺牲缺陷槽。 版权所有（C）2005，JPO＆NCIPI

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