公开(公告)号：EP1790003A4

公开(公告)日：2011-01-12

申请号：EP05784302

申请日：2005-08-04

Applicant: IBM

Inventor： BEDELL STEPHEN W ,  CHEN HUAJIE ,  FOGEL KEITH ,  MITCHELL RYAN M ,  SADANA DEVENDRA K

IPC: H01L21/36 ,  H01L21/02 ,  H01L21/20 ,  H01L31/117

CPC classification number: H01L29/1054 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02507 ,  H01L21/02532

公开(公告)号：EP1479103A4

公开(公告)日：2005-02-09

申请号：EP03731957

申请日：2003-01-16

Applicant: IBM

Inventor： BEDELL STEPHEN W ,  CHU JACK O ,  FOGEL KEITH E ,  KOESTER STEPHEN J ,  SADANA DEVENDRA K ,  OTT JOHN ALBRECHT

IPC: H01L27/08 ,  H01L21/02 ,  H01L21/20 ,  H01L21/225 ,  H01L21/324 ,  H01L21/337 ,  H01L21/762 ,  H01L27/12 ,  H01L29/786 ,  H01L21/331

CPC classification number: H01L21/76243 ,  H01L21/02378 ,  H01L21/02381 ,  H01L21/02488 ,  H01L21/02532 ,  H01L21/02612 ,  H01L21/2251 ,  H01L21/324 ,  H01L27/1203 ,  H01L29/66916 ,  Y10S438/938 ,  Y10T428/12674 ,  Y10T428/265 ,  Y10T428/31848

Abstract: A method of forming a thin, high-quality relaxed SiGe-on-insulator substrate (10) material is provided which first includes forming a SiGe or pure Ge layer on a surface of a first single crystal Si layer (14) which is present atop a barrier layer (12) that is resistant to the diffusion of Ge. Optionally forming a Si cap layer (18) over the SiGe or pure Ge layer (16), and thereafter heating the various layers at a temperature which permits interdiffusion of Ge throughtout the first single crystal Si layer (14), the optional Si cap (18) and the SiGe or pure Ge layer (16) thereby forming a substantially relaxed, single crystal SiGe layer atop the barrier layer (12). Additional SiGe regrowth and/or formation of a strained epi-Si layer may follow the above steps. SiGe-on-insulator substrate materials as well as structures including at least the SiGe-on-insulator substrate material are also disclosed herein.

Abstract translation: 提供了一种形成薄的，高品质的弛豫SiGe绝缘体上的基板材料的方法，其首先包括形成第一单晶Si层的表面上的SiGe或纯Ge层，其存在的顶上即耐阻挡层 到Ge的扩散。 OPTIONALLY形成在SiGe或纯Ge层中的Si间隙层，并随后在其允许的Ge的相互扩散在整个第一单晶Si层的温度下加热的各种层，任选的Si盖和SiGe或纯Ge层，从而形成 基本松弛，单晶SiGe层在阻挡层上。 额外的SiGe再生长和/或形成的应变外延Si层的可遵循上述步骤。 上SiGe绝缘体基板材料以及包含结构至少在SiGe绝缘体上的基板材料，因此是在盘游离缺失。

公开(公告)号：EP1709671A4

公开(公告)日：2010-06-16

申请号：EP04703076

申请日：2004-01-16

Applicant: IBM

Inventor： CHEN HUAJIE ,  BEDELL STEPHEN W ,  SADANA DEVENDRA K ,  MOCUTA DAN M

IPC: H01L21/331 ,  H01L21/20 ,  H01L21/205 ,  H01L21/316 ,  H01L21/762 ,  H01L21/84 ,  H01L29/10 ,  H01L29/786

CPC classification number: H01L21/76256 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02532 ,  H01L21/02664 ,  H01L21/31658 ,  H01L21/84 ,  H01L29/1054 ,  H01L29/78687

公开(公告)号：EP1779422A4

公开(公告)日：2007-08-01

申请号：EP05713741

申请日：2005-02-16

Applicant: IBM

Inventor： CHEN HUAJIE ,  BEDELL STEPHEN W

IPC: H01L21/76 ,  H01L21/205 ,  H01L21/762

CPC classification number: H01L21/76254 ,  Y10S438/91

Abstract: A method is disclosed for forming a semiconductor wafer having a strained Si or SiGe layer on an insulator layer. The method produces a structure having a SiGe buffer layer (43) between the insulator layer (45) and the strained Si/SiGe layer (42), but eliminates the need for Si epitaxy after bonding. The method also eliminates interfacial contamination between strained Si and SiGe buffer layer, and allows the formation of SVSiGe layers having a total thickness exceeding the critical thickness of the strained Si layer.

公开(公告)号：JP2004363592A

公开(公告)日：2004-12-24

申请号：JP2004158994

申请日：2004-05-28

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： SHAHIDI GHAVAM G ,  BEDELL STEPHEN W ,  SADANA DEVENDRA K ,  FOGEL KEITH E

IPC: H01L27/08 ,  H01L21/02 ,  H01L21/20 ,  H01L21/265 ,  H01L21/762 ,  H01L27/12

CPC classification number: H01L21/76243 ,  H01L21/26506 ,  H01L21/76267 ,  Y10T428/12674 ,  Y10T428/12681

Abstract: PROBLEM TO BE SOLVED: To provide a method of forming a substantially relaxed high-quality SiGe-on-insulator substrate material using SIMOX and Ge interdiffusion. SOLUTION: In order to form an injection rich area in a Si-containing substrate, ions are injected into Si-containing substrate at the beginning. The inplanted-ion rich region has sufficient ion concentration so that a barrier layer to disturb Ge diffusion is formed during annealing at a high temperature. Next, Ge-containing layer is formed on a surface of the Si-containing substrate, and then a heating process is performed at a temperature that enables the formation of a barrier layer, and the Ge interdiffusion. This allows a substantially relaxed single-crystal SiGe layer to be formed on the barrier layer. COPYRIGHT: (C)2005,JPO&NCIPI

公开(公告)号：JP2011082519A

公开(公告)日：2011-04-21

申请号：JP2010226294

申请日：2010-10-06

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： LIN CHUNG-HSUN ,  BEDELL STEPHEN W ,  CHANG JOSEPHINE B

IPC: H01L29/786 ,  H01L21/336 ,  H01L21/8238 ,  H01L27/08 ,  H01L27/092

CPC classification number: H01L29/66477 ,  H01L21/8238 ,  H01L21/823807 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/6653 ,  H01L29/66628 ,  H01L29/66651 ,  H01L29/66772 ,  H01L29/7843 ,  H01L29/7849

Abstract: PROBLEM TO BE SOLVED: To provide an integrated circuit having silicon on a stress liner, and its manufacturing method. SOLUTION: The method comprises a step of preparing a semiconductor substrate comprising an outer semiconductor layer and an embedded sacrifice layer under the outer semiconductor layer, and a step of removing at least a portion of the embedded sacrifice layer to form a void within the semiconductor substrate. The method further comprises a step of depositing a material in the void to form the stress liner, and a step of forming a transistor on the outer semiconductor layer of the semiconductor substrate. The outer semiconductor layer separates the transistor from the stress liner. The semiconductor substrate includes isolation regions, and the removing step includes a step of forming recesses in the isolation regions, and a step of removing at least a portion of the embedded sacrifice layer via these recesses. The depositing step includes a step of depositing a material in the void via the recesses 46. End caps 60 are formed in the recesses 46 contacting with ends of the stress liner. COPYRIGHT: (C)2011,JPO&INPIT

Abstract translation: 要解决的问题：提供一种在应力衬垫上具有硅的集成电路及其制造方法。 解决方案：该方法包括制备半导体衬底的步骤，该半导体衬底包括在外部半导体层下面的外部半导体层和嵌入的牺牲层，以及去除至少一部分嵌入的牺牲层以在其中形成空隙的步骤 半导体衬底。 该方法还包括在空隙中沉积材料以形成应力衬垫的步骤，以及在半导体衬底的外半导体层上形成晶体管的步骤。 外半导体层将晶体管与应力衬垫分开。 半导体衬底包括隔离区域，并且去除步骤包括在隔离区域中形成凹部的步骤，以及通过这些凹部去除嵌入的牺牲层的至少一部分的步骤。 沉积步骤包括通过凹部46将材料沉积在空隙中的步骤。在与应力衬垫的端部接触的凹部46中形成端盖60。 版权所有（C）2011，JPO＆INPIT

公开(公告)号：WO2004109776A3

公开(公告)日：2005-05-19

申请号：PCT/US2004016903

申请日：2004-05-28

Applicant: IBM ,  BEDELL STEPHEN W ,  CHEN HUAJIE ,  FOGEL KEITH E ,  SADANA DEVENDRA K

Inventor： BEDELL STEPHEN W ,  CHEN HUAJIE ,  FOGEL KEITH E ,  SADANA DEVENDRA K

IPC: H01L21/20 ,  H01L21/762 ,  H01L21/306

CPC classification number: H01L21/7624 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/02664 ,  Y10T428/12674

Abstract: The present invention provides a method of fabricating a SiGe-on-insulator substrate in which lattice engineering is employed to decouple the interdependence between SiGe thickness, Ge fraction and strain relaxation. The method includes providing a SiGe-on-insulator substrate material comprising a SiGe alloy layer having a selected in-plane lattice parameter, a selected thickness parameter and a selected Ge content parameter, wherein the selected in-plane lattice parameter has a constant value and one or both of the other parameters, i.e., thickness or Ge content, have adjustable values; and adjusting one or both of the other parameters to final selected values, while maintaining the selected in-plane lattice parameter. The adjusting is achieved utilizing either a thinning process or a thermal dilution process depending on which parameters are fixed and which are adjustable.

Abstract translation: 本发明提供了一种制造绝缘体上硅衬底的方法，其中使用晶格工程来去耦合SiGe厚度，Ge分数和应变松弛之间的相互依赖性。 该方法包括提供一种绝缘体上硅衬底材料，其包括具有选定的面内晶格参数的SiGe合金层，选定的厚度参数和所选择的Ge含量参数，其中所选择的面内晶格参数具有恒定值， 一个或两个其他参数，即厚度或Ge含量，具有可调整的值; 并且在保持所选择的平面内晶格参数的同时将其他参数中的一个或两个调整为最终选择的值。 根据哪些参数是固定的，哪些是可调节的，利用稀化过程或热稀释过程实现调节。

公开(公告)号：WO2007130333A2

公开(公告)日：2007-11-15

申请号：PCT/US2007010411

申请日：2007-04-30

Applicant: IBM ,  BEDELL STEPHEN W ,  DESOUZA JOEL P ,  REN ZHIBIN ,  REZNICEK ALEXANDER ,  SADANA DEVENDRA K ,  SAENGER KATHERINE L ,  SHAHIDI GHAVAM

Inventor： BEDELL STEPHEN W ,  DESOUZA JOEL P ,  REN ZHIBIN ,  REZNICEK ALEXANDER ,  SADANA DEVENDRA K ,  SAENGER KATHERINE L ,  SHAHIDI GHAVAM

IPC: H01L21/8234

CPC classification number: H01L29/66628 ,  H01L21/26513 ,  H01L21/324 ,  H01L21/823814 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/165 ,  H01L29/66636 ,  H01L29/66772 ,  H01L29/7848 ,  H01L29/78618 ,  H01L29/78684 ,  Y10S438/909 ,  Y10S438/943

Abstract: This invention teaches methods of combining ion implantation steps with in situ or ex situ heat treatments to avoid and/or minimize implant-induced amorphization (a potential problem for source/drain (SfD) regions in FETs in ultrathin silicon on insulator layers) and implant-induced plastic relaxation of strained S/D regions (a potential problem for strained channel FETs in which the channel strain is provided by embedded S/D regions lattice mismatched with an underlying substrate layer). In a first embodiment, ion implantation is combined with in situ heat treatment by performing the ion implantation at elevated temperature. In a second embodiment, ion implantation is combined withex situ heat treatments in a "divided-dose-anneal-in-between" (DDAB) scheme that avoids the need for tooling capable of performing hot implants.

Abstract translation: 本发明教导了将离子注入步骤与原位或非原位热处理组合以避免和/或最小化植入物诱导的非晶化（在绝缘体上的超薄硅层中的FET中的源/漏（SfD）区域的潜在问题）和植入物 诱导的应变S / D区域的塑性弛豫（对于通道应变由嵌入的S / D区域与下面的基底层不匹配而提供的应变通道FET的潜在问题）。 在第一实施例中，通过在升高的温度下进行离子注入将离子注入与原位热处理组合。 在第二实施例中，离子注入在“分剂量退火中间”（DDAB）方案中组合了原位热处理，避免了对能够进行热植入的加工的需要。

公开(公告)号：JP2009033196A

公开(公告)日：2009-02-12

申请号：JP2008258479

申请日：2008-10-03

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： BEDELL STEPHEN W ,  FOGEL KEITH E ,  SADANA DEVENDRA K

IPC: H01L21/20 ,  H01L29/161 ,  H01L21/265 ,  H01L21/762

CPC classification number: H01L21/76243 ,  H01L21/02378 ,  H01L21/02381 ,  H01L21/02488 ,  H01L21/02532 ,  H01L21/02664 ,  Y10S438/933

Abstract: PROBLEM TO BE SOLVED: To provide a method for forming a relaxed SiGe-on-insulator substrate having improved relaxation, significantly lower defect density, and improved surface quality.
SOLUTION: The method includes a step for forming an SiGe alloy layer on a surface of a first single crystal Si layer. The first single crystal Si layer has an interface with an underlay barrier layer having resistance to Ge diffusion. Next, ions are implanted into the structure, the ions forming defects by which mechanical decoupling is achieved at the interface or vicinity of the interface; then a heating step is performed to the structure including the implanted ions, by which mutual diffusion of Ge through the first single crystal Si layer and SiGe layer is achieved; thereby a SiGe layer that is substantially relaxed single crystal and homogenous is formed on the barrier layer. A SiGe-on-insulator having improved properties and a heterostructure including it are also provided.
COPYRIGHT: (C)2009,JPO&INPIT

Abstract translation: 解决的问题：提供一种形成松弛的绝缘体上硅衬底的方法，其具有改进的松弛，显着降低缺陷密度和改进的表面质量。 解决方案：该方法包括在第一单晶Si层的表面上形成SiGe合金层的步骤。 第一单晶Si层具有与Ge扩散性有抵抗性的底层阻挡层的界面。 接下来，将离子注入到结构中，离子形成缺陷，通过该缺陷在界面的界面或附近实现机械解耦; 然后对包括注入离子的结构进行加热步骤，由此实现Ge通过第一单晶Si层和SiGe层的相互扩散; 从而在阻挡层上形成基本上松弛的单晶并均匀的SiGe层。 还提供了具有改进性能的绝缘体上硅和包括其的异质结构。 版权所有（C）2009，JPO＆INPIT

公开(公告)号：JP2005079601A

公开(公告)日：2005-03-24

申请号：JP2004256027

申请日：2004-09-02

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： BEDELL STEPHEN W ,  CHEN HUAJIE ,  FOGEL KEITH E ,  SADANA DEVENDRA K

IPC: H01L29/161 ,  C30B29/52 ,  C30B31/02 ,  H01L21/02 ,  H01L21/20 ,  H01L21/205 ,  H01L21/762 ,  H01L21/8238 ,  H01L27/12 ,  H01L29/04

CPC classification number: H01L21/7624 ,  C30B29/52 ,  C30B31/02 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/02694 ,  Y10T428/24917

Abstract: PROBLEM TO BE SOLVED: To provide a manufacturing method for making a metastable strained SiGe layer. SOLUTION: The metastable SiGe layer is made by the method which includes a process that a layer containing Ge is formed on a surface of a layer disposed on a barrier layer to Ge diffusion containing Si in its upper surface portion thickness of 500 Å or less, and a process that a substantially metastable SiGe layer showing relaxation resistive property on the barrier layer is formed by heating the above-mentioned respective layers at the temperature enabling Ge to diffuse through the layer containing Si in its upper surface portion and the layer containing Ge mutually. COPYRIGHT: (C)2005,JPO&NCIPI

Abstract translation: 要解决的问题：提供一种制造亚稳态应变SiGe层的制造方法。 解决方案：亚稳态SiGe层是通过以下方法制成的，该方法包括：在设置在阻挡层上的层的表面上形成含有Ge的层，其上表面部分厚度为含有Si的Ge扩散 并且通过在使Ge能够通过其上表面部分中含有Si的层扩散的温度下加热上述各层来形成在阻挡层上显示松弛电阻性质的基本上亚稳态的SiGe层的工艺， 包含Ge相互。 版权所有（C）2005，JPO＆NCIPI