中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

45 records (took 0.019 seconds)

    SINGLE-JUNCTION PHOTOVOLTAIC CELL
    1.
    发明申请
    SINGLE-JUNCTION PHOTOVOLTAIC CELL 审中-公开
    单晶光伏电池

    公开(公告)号：WO2011106204A2

    公开(公告)日：2011-09-01

    申请号：PCT/US2011024949

    申请日：2011-02-16

    Applicant: IBM ,  BEDELL STEPHEN W ,  FOGEL KEITH E ,  SOSA CORTES NORMA E ,  SADANA DEVENDRA ,  SHAHRJERDI DAVOOD ,  WACASER BRENT A

    Inventor： BEDELL STEPHEN W ,  FOGEL KEITH E ,  SOSA CORTES NORMA E ,  SADANA DEVENDRA ,  SHAHRJERDI DAVOOD ,  WACASER BRENT A

    IPC: H01L31/042 ,  H01L31/06

    CPC classification number: H01L31/0304 ,  H01L31/0725 ,  H01L31/074 ,  H01L31/075 ,  H01L31/076 ,  H01L31/184 ,  H01L31/1892 ,  Y02E10/548

    Abstract: A method for forming a single-junction photovoltaic cell includes forming a dopant layer on a surface of a semiconductor substrate; diffusing the dopant layer into the semiconductor substrate to form a doped layer of the semiconductor substrate; forming a metal layer over the doped layer, wherein a tensile stress in the metal layer is configured to cause a fracture in the semiconductor substrate; removing a semiconductor layer from the semiconductor substrate at the fracture; and forming the single-junction photovoltaic cell using the semiconductor layer. A single-junction photovoltaic cell includes a doped layer comprising a dopant diffused into a semiconductor substrate; a patterned conducting layer formed on the doped layer; a semiconductor layer comprising the semiconductor substrate located on the doped layer on a surface of the doped layer opposite the patterned conducting layer; and an ohmic contact layer formed on the semiconductor layer.

    Abstract translation: 一种形成单结光伏电池的方法包括在半导体衬底的表面上形成掺杂剂层; 将掺杂剂层扩散到半导体衬底中以形成半导体衬底的掺杂层; 在所述掺杂层上形成金属层，其中所述金属层中的拉伸应力构造成在所述半导体衬底中引起断裂; 在断裂时从半导体衬底去除半导体层; 以及使用半导体层形成单结光伏电池。 单结光伏电池包括掺杂剂，该掺杂层包含扩散到半导体衬底中的掺杂剂; 形成在掺杂层上的图案化导电层; 半导体层，其包括位于掺杂层的与图案化导电层相对的表面上的掺杂层上的半导体衬底; 以及形成在半导体层上的欧姆接触层。

    DUAL-GATE BIO/CHEM SENSOR
    2.
    发明申请
    DUAL-GATE BIO/CHEM SENSOR 审中-公开
    双门生物/ CHEM传感器

    公开(公告)号：WO2014062285A2

    公开(公告)日：2014-04-24

    申请号：PCT/US2013054601

    申请日：2013-08-13

    Applicant: IBM

    Inventor： BEDELL STEPHEN W ,  HEKMATSHOARTABARI BAHMAN ,  SHAHIDI GHAVAM G ,  SHAHRJERDI DAVOOD

    IPC: H01L21/336

    CPC classification number: H01L29/78648 ,  H01L21/84

    Abstract: A dual gate extremely thin semiconductor-on-insulator transistor with asymmetric gate dielectrics is provided. This structure can improve the sensor detection limit and also relieve the drift effects. Detection is performed at a constant current mode while the species will be detected at a gate electrode with a thin equivalent oxide thickness (EOT) and the gate bias will be applied to the second gate electrode with thicker EOT to maintain current flow through the transistor. As a result, a small change in the charge on the first electrode with the thin EOT will be translated into a larger voltage on the gate electrode with the thick EOT to sustain the current flow through the transistor. This allows a reduction of the sensor dimension and therefore an increase in the array size. The dual gate structure further includes cavities, i.e., microwell arrays, for chemical sensing.

    Abstract translation: 提供了具有非对称栅极电介质的双栅非常薄的绝缘体上半导体晶体管。 这种结构可以提高传感器的检测极限，也可以减轻漂移的影响。 以恒定电流模式进行检测，同时将在具有薄当量氧化物厚度（EOT）的栅电极处检测物种，并且将栅极偏压施加到具有较大EOT的第二栅电极，以保持电流流过晶体管。 结果，具有薄EOT的第一电极上的电荷的小的变化将被转换成具有较厚EOT的栅电极上的较大电压，以维持通过晶体管的电流。 这允许减小传感器尺寸并因此减小阵列尺寸。 双栅极结构还包括用于化学感测的空腔，即微孔阵列。

    REMOVAL OF STRESSOR LAYER FROM A SPALLED LAYER AND METHOD OF MAKING A BIFACIAL SOLAR CELL USING THE SAME
    3.
    发明申请
    REMOVAL OF STRESSOR LAYER FROM A SPALLED LAYER AND METHOD OF MAKING A BIFACIAL SOLAR CELL USING THE SAME 审中-公开
    从粉末层去除压力层和使用其制造双极太阳能电池的方法

    公开(公告)号：WO2013181117A3

    公开(公告)日：2014-04-03

    申请号：PCT/US2013042772

    申请日：2013-05-24

    Applicant: IBM

    Inventor： BEDELL STEPHEN W ,  FOGEL KEITH E ,  HEKMATSHOARTABARI BAHMAN ,  LAURO PAUL A ,  LI NING ,  SADANA DEVENDRA K ,  SHAHIDI GHAVAM G ,  SHAHRJERDI DAVOOD

    IPC: H01L31/18

    CPC classification number: H01L31/0684 ,  H01L21/02002 ,  H01L31/1896 ,  Y02E10/547

    Abstract: A stressor layer used in a controlled spalling method is removed through the use of a cleave layer that can be fractured or dissolved. The cleave layer is formed between a host semiconductor substrate and the metal stressor layer. A controlled spalling process separates a relatively thin residual host substrate layer from the host substrate. Following attachment of a handle substrate to the residual substrate layer or other layers subsequently formed thereon, the cleave layer is dissolved or otherwise compromised to facilitate removal of the stressor layer. Such removal allows the fabrication of a bifacial solar cell.

    Abstract translation: 以受控剥落方式使用的应力层通过使用可以断裂或溶解的裂开层去除。 在主体半导体衬底和金属应力层之间形成切割层。 受控的剥落过程将相对薄的残余主体衬底层与主体衬底分离。 在将手柄衬底附接到残留衬底层或随后在其上形成的其它层之后，解理层被溶解或以其他方式受到损害以便于去除应力层。 这种去除允许制造双面太阳能电池。

    SPALLING FOR A SEMICONDUCTOR SUBSTRATE
    4.
    发明申请
    SPALLING FOR A SEMICONDUCTOR SUBSTRATE 审中-公开
    用于半导体衬底的分离

    公开(公告)号：WO2011106203A3

    公开(公告)日：2011-11-17

    申请号：PCT/US2011024948

    申请日：2011-02-16

    Applicant: IBM ,  BEDELL STEPHEN W ,  FOGEL KEITH E ,  LAURO PAUL A ,  SADANA DEVENDRA ,  SHAHRJERDI DAVOOD

    Inventor： BEDELL STEPHEN W ,  FOGEL KEITH E ,  LAURO PAUL A ,  SADANA DEVENDRA ,  SHAHRJERDI DAVOOD

    IPC: H01L21/304 ,  B28D5/00

    CPC classification number: H01L31/075 ,  H01L21/02002 ,  H01L31/0725 ,  H01L31/074 ,  H01L31/076 ,  H01L31/184 ,  H01L31/1892 ,  Y02E10/548

    Abstract: A method for spalling a layer from an ingot of a semiconductor substrate includes forming a metal layer on the ingot of the semiconductor substrate, wherein a tensile stress in the metal layer is configured to cause a fracture in the ingot; and removing the layer from the ingot at the fracture. A system for spalling a layer from an ingot of a semiconductor substrate includes a metal layer formed on the ingot of the semiconductor substrate, wherein a tensile stress in the metal layer is configured to cause a fracture in the ingot, and wherein the layer is configured to be removed from the ingot at the fracture.

    Abstract translation: 一种用于从半导体衬底的晶锭剥落层的方法包括：在半导体衬底的晶块上形成金属层，其中金属层中的拉伸应力被配置为引起晶块中的断裂; 并在裂缝处从锭块中去除层。 用于从半导体衬底的晶锭剥落层的系统包括形成在半导体衬底的晶锭上的金属层，其中金属层中的拉应力被配置为引起晶块中的断裂，并且其中该层被配置 在骨折处从锭块中移出。

    Selektives epitaxiales Anwachsen von Silicium bei niedriger Temperatur zur Integration von Einheiten
    5.
    发明专利
    Selektives epitaxiales Anwachsen von Silicium bei niedriger Temperatur zur Integration von Einheiten 未知

    公开(公告)号：DE112012000962B4

    公开(公告)日：2020-11-12

    申请号：DE112012000962

    申请日：2012-01-26

    Applicant: IBM

    Inventor： HEKMATSHOAR-TABARI BAHMAN ,  KHAKIFIROOZ ALI ,  REZNICEK ALEXANDER ,  SADANA DEVENDRA K ,  SHAHIDI GHAVAM G ,  SHAHRJERDI DAVOOD

    IPC: H01L21/205 ,  C23C16/24 ,  C23C16/44 ,  C30B25/04 ,  H01L21/32

    Abstract: Epitaxieverfahren, aufweisend:Bereitstellen (502) eines kristallinen Substratmaterials (102);Anwachsen (504) eines Isolators (108) auf dem Substratmaterial (102);Öffnen (506) des Isolators (108), um frei liegende Bereiche des Substratmaterials (102) zu bilden;Abscheiden (512) von Silicium auf den frei liegenden Bereichen des Substratmaterials, um in einem Niedertemperaturverfahren auf den frei liegenden Bereichen epitaxiales Silicium (302) zu bilden und in anderen als den frei liegenden Bereichen nicht epitaxiales Silicium (310) zu bilden, wobei eine Abscheidungstemperatur weniger als 250 °C beträgt;Einbringen (518) eines Dotierstoffs mit einem Gasverhältnis, wodurch ein dotiertes epitaxiales Silicium bereitgestellt wird, wobei eine hohe Dotierstoffaktivierung höher als 1 x 1020cm-3erhalten wird; undÄtzen des nicht epitaxialen Siliciums unter Verwendung eines Plasmas, um die epitaxiale Abscheidung von Silicium über den frei liegenden Bereichen zu unterstützen,wobei das selektive epitaxiale Anwachsen durch Abwechseln der Abscheidungs- und Ätzschritte bereitgestellt wird.

    Edge-exclusion spalling method for removing substrate material
    9.
    发明专利
    Edge-exclusion spalling method for removing substrate material 未知

    公开(公告)号：GB2492444A

    公开(公告)日：2013-01-02

    申请号：GB201208147

    申请日：2012-05-10

    Applicant: IBM

    Inventor： BEDELL STEPHEN ,  FOGEL KEITH ,  LAURO PAUL ,  CORTES NORMA EDITH SOSA ,  SHAHRJERDI DAVOOD ,  SADANA DEVENDRA

    IPC: H01L31/18

    Abstract: A method to minimize edge-related substrate breakage during spalling using an edge-exclusion region (14) where the stressor layer (16) is either non-present (excluded either during deposition or removed afterwards) or present but significantly non-adhered to the substrate surface in the exclusion region is provided. In a preferred embodiment of the present invention, the method includes forming an edge exclusion material (14) on an upper surface and near an edge of a base substrate (10â â ). A stressor layer (16) is then formed on exposed portions of the upper surface of the base substrate (10â â ) and atop the edge exclusion material (14). A portion (10â ) of the base substrate that is located beneath the stressor layer and which is not covered by the edge exclusion material is then spalled and separated from the bulk of the substrate. The material is removed from the substrate by stresses caused by the stressor layer. An adhesive layer (15) can be formed between the substrate and stressor layer. This method improves the reusability of the substrate.

Patent Agency Ranking