公开(公告)号：EP1665334A4

公开(公告)日：2011-02-23

申请号：EP04756338

申请日：2004-06-29

Applicant: IBM

Inventor： PARK HEEMYOUNG ,  AGNELLO PAUL D ,  GILBERT PERCY V ,  LEE BYOUNG H ,  O'NEIL PATRICIA A ,  SHAHIDI GHAVAM G ,  WELSER JEFFREY J

IPC: H01L21/8234 ,  H01L21/336 ,  H01L21/425 ,  H01L21/4763 ,  H01L21/84 ,  H01L27/12 ,  H01L29/423 ,  H01L29/45 ,  H01L29/49 ,  H01L29/786

CPC classification number: H01L29/66772 ,  H01L21/84 ,  H01L29/458 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/66628 ,  H01L29/78621

公开(公告)号：WO2014062285A2

公开(公告)日：2014-04-24

申请号：PCT/US2013054601

申请日：2013-08-13

Applicant: IBM

Inventor： BEDELL STEPHEN W ,  HEKMATSHOARTABARI BAHMAN ,  SHAHIDI GHAVAM G ,  SHAHRJERDI DAVOOD

IPC: H01L21/336

CPC classification number: H01L29/78648 ,  H01L21/84

Abstract: A dual gate extremely thin semiconductor-on-insulator transistor with asymmetric gate dielectrics is provided. This structure can improve the sensor detection limit and also relieve the drift effects. Detection is performed at a constant current mode while the species will be detected at a gate electrode with a thin equivalent oxide thickness (EOT) and the gate bias will be applied to the second gate electrode with thicker EOT to maintain current flow through the transistor. As a result, a small change in the charge on the first electrode with the thin EOT will be translated into a larger voltage on the gate electrode with the thick EOT to sustain the current flow through the transistor. This allows a reduction of the sensor dimension and therefore an increase in the array size. The dual gate structure further includes cavities, i.e., microwell arrays, for chemical sensing.

Abstract translation: 提供了具有非对称栅极电介质的双栅非常薄的绝缘体上半导体晶体管。 这种结构可以提高传感器的检测极限，也可以减轻漂移的影响。 以恒定电流模式进行检测，同时将在具有薄当量氧化物厚度（EOT）的栅电极处检测物种，并且将栅极偏压施加到具有较大EOT的第二栅电极，以保持电流流过晶体管。 结果，具有薄EOT的第一电极上的电荷的小的变化将被转换成具有较厚EOT的栅电极上的较大电压，以维持通过晶体管的电流。 这允许减小传感器尺寸并因此减小阵列尺寸。 双栅极结构还包括用于化学感测的空腔，即微孔阵列。

公开(公告)号：JP2011181955A

公开(公告)日：2011-09-15

申请号：JP2011111716

申请日：2011-05-18

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： BENDERNAGEL ROBERT E ,  CHO KWANG SU ,  BIJAN DAVARI ,  FOGEL KEITH E ,  SADANA DEVENDRA K ,  SHAHIDI GHAVAM G ,  TIWARY SANDIP

IPC: H01L27/12 ,  H01L21/02 ,  H01L21/20

Abstract: PROBLEM TO BE SOLVED: To form a patterned silicon-on-insulator (SOI)/silicon-on-nothing (SON) composite structure by a porous Si technique.
SOLUTION: A patterned SOI/SON composite structure and a method of forming the same are provided. In the SOI/SON composite structure, a patterned SOI/SON structure is sandwiched between an Si overlayer and a semiconductor substrate. The method of forming the patterned SOI/SON composite structure includes a shared processing treatment step wherein both SOI and SON structures are formed. This invention further provides a method of forming a composite structure including an embedded conductive/SON structure, and a method of forming a composite structure including only an embedded void plane.
COPYRIGHT: (C)2011,JPO&INPIT

Abstract translation: 要解决的问题：通过多孔Si技术形成图案化的绝缘体上硅（SOI）/无硅（SON）复合结构。 解决方案：提供了图案化的SOI / SON复合结构及其形成方法。 在SOI / SON复合结构中，图案化SOI / SON结构夹在Si覆层和半导体衬底之间。 形成图案化SOI / SON复合结构的方法包括形成SOI和SON结构的共同处理处理步骤。 本发明还提供一种形成包括嵌入式导电/ SON结构的复合结构的方法，以及形成仅包括嵌入的空隙平面的复合结构的方法。 版权所有（C）2011，JPO＆INPIT

公开(公告)号：JP2006032962A

公开(公告)日：2006-02-02

申请号：JP2005204182

申请日：2005-07-13

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： BEDELL STEPHEN W ,  CHEN HUAJIE ,  FOGEL KEITH E ,  SADANA DEVENDRA K ,  SHAHIDI GHAVAM G

IPC: H01L21/20

CPC classification number: H01L21/26506 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/02694

Abstract: PROBLEM TO BE SOLVED: To provide a method for suppressing the formation of flat surface defects, such as stacking faults and microtwins in a relaxed SiGe alloy layer.
SOLUTION: There is disclosed the method of manufacturing a substantially-relaxed SiGe alloy layer, in which flat surface defect density is decreased. The method comprises the steps of forming a strained Ge-containing layer on the front surface of an Si-containing substrate, implanting ions into the interface of the Ge-containing layer/the Si-containing substrate or under the interface, and forming the substantially-relaxed SiGe alloy layer, in which the flat surface defect density is decreased. Further, there are also provided a substantially relaxed SiGe-on-insulator, having an SiGe layer in which the flat surface defect density is decreased, and a heterostructure comprising the insulator.
COPYRIGHT: (C)2006,JPO&NCIPI

Abstract translation: 要解决的问题：提供一种抑制在弛豫SiGe合金层中形成平坦表面缺陷的方法，例如层叠缺陷和微丝。 解决方案：公开了制造基本上松弛的SiGe合金层的方法，其中平坦表面缺陷密度降低。 该方法包括以下步骤：在含Si衬底的前表面上形成应变的含锗层，将离子注入含Ge层/含Si衬底的界面或界面之下，并形成基本上 不透明的SiGe合金层，其中平坦表面缺陷密度降低。 此外，还提供了具有其中平坦表面缺陷密度降低的SiGe层和包含绝缘体的异质结构的基本上松弛的绝缘体上SiGe。 版权所有（C）2006，JPO＆NCIPI

公开(公告)号：JP2006049897A

公开(公告)日：2006-02-16

申请号：JP2005219835

申请日：2005-07-29

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： DAINE C BOYD ,  HOLT JUDSON R ,  LEONG MEIKEI ,  MO RENEE T ,  REN ZHIBIN ,  SHAHIDI GHAVAM G

IPC: H01L29/786 ,  H01L21/336 ,  H01L21/76 ,  H01L21/762 ,  H01L21/8238 ,  H01L27/08 ,  H01L27/092

CPC classification number: H01L27/1203 ,  H01L21/76283 ,  H01L21/823892 ,  H01L21/84 ,  H01L29/66772 ,  H01L29/78609 ,  H01L29/78618 ,  H01L29/78696

Abstract: PROBLEM TO BE SOLVED: To provide a method for manufacturing a super-steep retrograde well field effect transistor device, and to provide an ultra-thin body FET device manufactured by the same.
SOLUTION: The method for manufacturing a super-steep retrograde well field effect transistor device starts with an SOI layer formed on a substrate, for example, an embedded oxide layer. The SOI layer is thinned so as to form an ultra-thin SOI layer. A separation trench is formed for dividing the SOI layer into an N ground layer region and a P ground layer region. The N and P ground layer regions formed in the SOI layer are doped with N-type and P-type dopants to a high concentration level. A semiconductor channel region is formed on the N and P ground layer regions. The source region and the drain region of the FET and the gate electrode stack on the channel region are formed. As desired, a diffusion retarding layer is formed between the SOI ground layer regions and the channel regions.
COPYRIGHT: (C)2006,JPO&NCIPI

Abstract translation: 要解决的问题：提供一种用于制造超陡逆向井场效应晶体管器件的方法，并提供由其制造的超薄体FET器件。 解决方案：用于制造超陡逆向井场效应晶体管器件的方法从形成在衬底上的SOI层，例如嵌入的氧化物层开始。 SOI层被薄化以形成超薄SOI层。 形成分离沟槽，用于将SOI层分成N个接地层区域和P个接地层区域。 形成在SOI层中的N和P接地层区域以高浓度水平掺杂有N型和P型掺杂剂。 在N和P接地层区域上形成半导体沟道区。 形成FET的源极区域和漏极区域以及沟道区域上的栅电极堆叠。 根据需要，在SOI接地层区域和沟道区域之间形成扩散延迟层。 版权所有（C）2006，JPO＆NCIPI

公开(公告)号：JP2002343883A

公开(公告)日：2002-11-29

申请号：JP2002096272

申请日：2002-03-29

Applicant: IBM

Inventor： PARK HEEMYONG ,  ASSADERAGHI FARIBORZ ,  AJMERA ATUL C ,  SHAHIDI GHAVAM G

IPC: H01L29/41 ,  H01L21/336 ,  H01L21/8238 ,  H01L27/08 ,  H01L27/092 ,  H01L29/417 ,  H01L29/45 ,  H01L29/786

Abstract: PROBLEM TO BE SOLVED: To provide a CMOS structure and a method of achieving self-aligned raised source/drain for CMOS structures on SOI without relying on selective epitaxial growth of silicon. SOLUTION: In this method, CMOS structures are provided by performing sacrificial oxidation so that oxidation occurs on the surface of both the SOI and BOX interfaces. This sacrificial oxidation allows oxide spacer formation for gate-to-source/drain isolation, which enables raised source/drain fabrication without increasing contact resistance.

公开(公告)号：JP2007142401A

公开(公告)日：2007-06-07

申请号：JP2006303404

申请日：2006-11-08

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： DOMINIC J SCHEPIS ,  LEE JUNEDONG ,  DEVENDRA K SADANA ,  SHAHIDI GHAVAM G

IPC: H01L21/76 ,  H01L21/02 ,  H01L21/20 ,  H01L23/52 ,  H01L27/12

CPC classification number: H01L21/84 ,  H01L21/76251 ,  H01L21/823807 ,  H01L21/823878 ,  H01L27/1203 ,  H01L27/1207 ,  H01L29/04

Abstract: PROBLEM TO BE SOLVED: To provide a substrate for semiconductor device including a plurality of semiconductor-on-insulator (SOI) wafers that are coupled with each other in a single stack. SOLUTION: The remote end of this stack includes a first SOI region with a first semiconductor layer of a certain thickness having a first surface orientation. The surface of this single stack can further comprise a non-SOI region or at least a second SOI region, or comprise both of them. This non-SOI region can comprise a bulk silicon extending through all insulator layers of the single stack and having a thickness different from that of a first silicon layer. A second SOI region has a second semiconductor layer having a thickness different from that of the first semiconductor layer or the surface orientation different from the first surface orientation, or both different. Thus, this substrate can permit the formation of different devices on the optimum substrate region with the different surface orientation, the different thickness, the different structure from the bulk or SOI, or the combination of these different ones. COPYRIGHT: (C)2007,JPO&INPIT

Abstract translation: 要解决的问题：提供一种包括在单个堆叠中彼此耦合的多个绝缘体上半导体（SOI）晶片的半导体器件的衬底。 解决方案：该堆叠的远端包括具有第一表面取向的具有一定厚度的第一半导体层的第一SOI区域。 该单个堆叠的表面可以进一步包括非SOI区域或至少第二SOI区域，或者包括它们两者。 该非SOI区域可以包括延伸穿过单个堆叠的所有绝缘体层并且具有与第一硅层的厚度不同的厚度的体硅。 第二SOI区域具有与第一半导体层的厚度不同的第二半导体层或与第一表面取向不同的表面取向，或者两者不同。 因此，该衬底可以允许在最佳衬底区域上形成不同的器件，其具有不同的表面取向，不同的厚度，与本体或SOI的不同结构，或这些不同的组合。 版权所有（C）2007，JPO＆INPIT

公开(公告)号：JP2004214628A

公开(公告)日：2004-07-29

申请号：JP2003396341

申请日：2003-11-26

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： HIIMYONGU PAAKU ,  LEE BYOUNG H ,  PAUL D AGUNERO ,  SCHEPIS DOMINIC J ,  SHAHIDI GHAVAM G

IPC: H01L21/28 ,  H01L21/00 ,  H01L21/336 ,  H01L21/76 ,  H01L21/762 ,  H01L21/8238 ,  H01L21/84 ,  H01L27/01 ,  H01L27/08 ,  H01L27/092 ,  H01L27/12 ,  H01L29/417 ,  H01L29/423 ,  H01L29/49 ,  H01L29/74 ,  H01L29/76 ,  H01L29/78 ,  H01L29/786 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC classification number: H01L29/78612 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/41783 ,  H01L29/66772

Abstract: PROBLEM TO BE SOLVED: To provide the structure of a CMOS device and a method for manufacturing the CMOS device.
SOLUTION: The manufacturing method comprises a process of sticking an SOI wafer 20 having prescribed thickness to the surface of a buried oxide (BOX) substrate 10, a process of forming a gate dielectric 25 on the surface of the SOI wafer 20, a process of forming a shallow trench isolation (STI) area 35 so as to form an almost round corner on the BOX substrate 10, a process of forming gate structure on the surface of the gate dielectric 25, a process of sticking a driving layer to the surface of the SOI wafer 20, a process for executing either one of N-type dopant implanting and P-type dopant implanting in the SOI wafer 20 and the implanting layer, and a process of forming a source/drain region 79(a) from the implanting layer and the SOI wafer 20. The source/drain region 79(a) has thickness larger than the prescribed thickness of the SOI wafer 20, and the gate dielectric is arranged lower than the STI region 35.
COPYRIGHT: (C)2004,JPO&NCIPI

公开(公告)号：JP2004363592A

公开(公告)日：2004-12-24

申请号：JP2004158994

申请日：2004-05-28

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： SHAHIDI GHAVAM G ,  BEDELL STEPHEN W ,  SADANA DEVENDRA K ,  FOGEL KEITH E

IPC: H01L27/08 ,  H01L21/02 ,  H01L21/20 ,  H01L21/265 ,  H01L21/762 ,  H01L27/12

CPC classification number: H01L21/76243 ,  H01L21/26506 ,  H01L21/76267 ,  Y10T428/12674 ,  Y10T428/12681

Abstract: PROBLEM TO BE SOLVED: To provide a method of forming a substantially relaxed high-quality SiGe-on-insulator substrate material using SIMOX and Ge interdiffusion. SOLUTION: In order to form an injection rich area in a Si-containing substrate, ions are injected into Si-containing substrate at the beginning. The inplanted-ion rich region has sufficient ion concentration so that a barrier layer to disturb Ge diffusion is formed during annealing at a high temperature. Next, Ge-containing layer is formed on a surface of the Si-containing substrate, and then a heating process is performed at a temperature that enables the formation of a barrier layer, and the Ge interdiffusion. This allows a substantially relaxed single-crystal SiGe layer to be formed on the barrier layer. COPYRIGHT: (C)2005,JPO&NCIPI

公开(公告)号：JP2003017709A

公开(公告)日：2003-01-17

申请号：JP2002123022

申请日：2002-04-24

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーション

Inventor： ASSADERAGHI FARIBORZ ,  CHEN TZE-CHIANG ,  MULLER PAUL K ,  EDWARD J NOWAKU ,  SHAHIDI GHAVAM G

IPC: H01L21/28 ,  H01L21/336 ,  H01L29/41 ,  H01L29/78 ,  H01L29/786

CPC classification number: H01L29/66757 ,  H01L29/66772 ,  H01L29/78618 ,  H01L29/78651 ,  H01L29/78675

Abstract: PROBLEM TO BE SOLVED: To provide a design capable of manufacturing a field-effect transistor which is fine in size and contains a sub-lithography channel length on an SOI wafer or a chip with a high degree of integration through a well-known and fully-developed process. SOLUTION: A short channel effect can be effectively restrained by the use of the impurity concentration of a steep gradient which can be accurately improved in shape and arranged at a proper position, and on the other hand, impurities are injected into a polysilicon seed adjacent to the conduction channel of a transistor and diffused into the conduction channel from the polysilicon seed to relax the allowance of a process. The polysilicon seed enables a polysilicon source/drain contact, which has a structure capable of reducing its current density and path length to an irreducible minimum and giving other mechanical advantages, to grow epitaxially from the polysilicon seed.

Abstract translation: 要解决的问题：提供一种能够制造尺寸精细并且在SOI晶片或具有高度集成度的芯片上的亚光刻通道长度通过公知的和完全的集成的场效应晶体管的设计 开发过程。 解决方案：通过使用可以精确改善形状并排列在适当位置的陡峭梯度的杂质浓度，可以有效地抑制短通道效应，另一方面，将杂质注入邻近的多晶硅晶种 晶体管的导电沟道，并且从多晶硅晶种扩散到导电沟道中以放宽工艺的余量。 多晶硅种子能够实现多晶硅源极/漏极接触，其具有能够将其电流密度和路径长度降低到不可约最小值并提供其它机械优点的结构，以从多晶硅种子外延生长。