公开(公告)号：BR9001125A

公开(公告)日：1991-03-05

申请号：BR9001125

申请日：1990-03-09

Applicant: IBM

Inventor： BLAKE ROBERT MARTIN ,  BOSSEN DOUGLAS CRAIG ,  CHEN CHIN-LONG ,  FIFIELD JOHN ATKINSON ,  KALTER HOWARD LEO ,  LO TIN-CHEE

IPC: G06F12/16 ,  G06F11/10 ,  G11C29/00

Abstract: In a memory system comprising a plurality of memory units (10) each of which possesses unit-level error correction capabilities (20) and each of which are tied to a system level error correction function (30), memory reliability is enhanced by providing means for fixing the output of one of the memory units at a fixed value in response to the occurrence of an uncorrectable error in one of the memory units. This counter-intuitive approach to the generation of forced hard errors nonetheless enhances overall memory system reliability since it enables the employment of the complement/recomplement algorithm which depends upon the presence of reproducible errors for proper operation. Thus, chip level error correction systems, which are increasingly desirable at high packaging densities, are employed in a way which does not interfere with system level error correction methods.

公开(公告)号：SG46485A1

公开(公告)日：1998-02-20

申请号：SG1996005030

申请日：1990-02-02

Applicant: IBM

Inventor： BLAKE ROBERT MARTIN ,  BOSSEN DOUGLAS CRAIG ,  CHEN CHIN-LONG ,  FIFIELD JOHN ATKINSON ,  KALTER HOWARD LEO

IPC: G06F11/10 ,  G06F12/16 ,  G06F11/00

Abstract: In a memory system comprising a plurality of memory units (10) each of which possesses unit-level error correction capabilities (20) and each of which are tied to a system level error correction function (30), memory reliability is enhanced by providing means (Fig. 2) for disabling the unit-level error correction capability, for example, in response to the occurrence of an uncorrectable error in one of the memory units. This counter-intuitive approach which disables an error correction function nonetheless enhances overall memory system reliability since it enables the employment of the complement/recomplement algorithm which depends upon the presence of reproducible errors for proper operation. Thus, chip level error correction systems, which are increasingly desirable at high packaging densities, are employed in a way which does not interfere with system level error correction methods.

公开(公告)号：NZ232466A

公开(公告)日：1992-08-26

申请号：NZ23246690

申请日：1990-02-09

Applicant: IBM

Inventor： BLAKE ROBERT MARTIN ,  BOSSEN DOUGLAS CRAIG ,  CHEN CHIN-LONG ,  FIFIELD JOHN ATKINSON ,  KALTER HOWARD LEO

IPC: G06F11/10 ,  G06F12/16 ,  G06F11/16 ,  G11C29/00

Abstract: In a memory system comprising a plurality of memory units (10) each of which possesses unit-level error correction capabilities (20) and each of which are tied to a system level error correction function (30), memory reliability is enhanced by providing means (Fig. 2) for disabling the unit-level error correction capability, for example, in response to the occurrence of an uncorrectable error in one of the memory units. This counter-intuitive approach which disables an error correction function nonetheless enhances overall memory system reliability since it enables the employment of the complement/recomplement algorithm which depends upon the presence of reproducible errors for proper operation. Thus, chip level error correction systems, which are increasingly desirable at high packaging densities, are employed in a way which does not interfere with system level error correction methods.

公开(公告)号：AU623490B2

公开(公告)日：1992-05-14

申请号：AU4939390

申请日：1990-02-09

Applicant: IBM

Inventor： BLAKE ROBERT MARTIN ,  BOSSEN DOUGLAS CRAIG ,  CHEN CHIN-LONG ,  FIFIELD JOHN ATKINSON ,  KALTER HOWARD LEO ,  LO TIN-CHEE

IPC: G06F12/16 ,  G06F11/10 ,  G06F12/00 ,  G06F11/00

Abstract: In a memory system comprising a plurality of memory units (10) each of which possesses unit-level error correction capabilities (20) and each of which are tied to a system level error correction function (30), memory reliability is enhanced by providing means for fixing the output of one of the memory units at a fixed value in response to the occurrence of an uncorrectable error in one of the memory units. This counter-intuitive approach to the generation of forced hard errors nonetheless enhances overall memory system reliability since it enables the employment of the complement/recomplement algorithm which depends upon the presence of reproducible errors for proper operation. Thus, chip level error correction systems, which are increasingly desirable at high packaging densities, are employed in a way which does not interfere with system level error correction methods.