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公开(公告)号：NZ232458A
公开(公告)日：1992-03-26
申请号：NZ23245890
申请日：1990-02-09
Applicant: IBM
Inventor： BLAKE ROBERT MARTIN , BOSSEN DOUGLAS CRAIG , CHEN CHIN-LONG , FIFIELD JOHN ATKINSON , KALTER HOWARD LEO , LO TIN-CHEE
Abstract: In a memory system comprising a plurality of memory units (10) each of which possesses unit-level error correction capabilities (20) and each of which are tied to a system level error correction function (30), memory reliability is enhanced by providing means for fixing the output of one of the memory units at a fixed value in response to the occurrence of an uncorrectable error in one of the memory units. This counter-intuitive approach to the generation of forced hard errors nonetheless enhances overall memory system reliability since it enables the employment of the complement/recomplement algorithm which depends upon the presence of reproducible errors for proper operation. Thus, chip level error correction systems, which are increasingly desirable at high packaging densities, are employed in a way which does not interfere with system level error correction methods.
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公开(公告)号：AU615373B2
公开(公告)日：1991-09-26
申请号：AU4939990
申请日：1990-02-09
Applicant: IBM
Inventor： BLAKE ROBERT MARTIN , BOSSEN DOUGLAS CRAIG , CHEN CHIN-LONG , FIFIELD JOHN ATKINSON , KALTER HOWARD LEO
Abstract: In a memory system comprising a plurality of memory units (10) each of which possesses unit-level error correction capabilities (20) and each of which are tied to a system level error correction function (30), memory reliability is enhanced by providing means (Fig. 2) for disabling the unit-level error correction capability, for example, in response to the occurrence of an uncorrectable error in one of the memory units. This counter-intuitive approach which disables an error correction function nonetheless enhances overall memory system reliability since it enables the employment of the complement/recomplement algorithm which depends upon the presence of reproducible errors for proper operation. Thus, chip level error correction systems, which are increasingly desirable at high packaging densities, are employed in a way which does not interfere with system level error correction methods.
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公开(公告)号：DE69021413T2
公开(公告)日：1996-03-21
申请号：DE69021413
申请日：1990-02-02
Applicant: IBM
Inventor： BLAKE ROBERT MARTIN , BOSSEN DOUGLAS CRAIG , CHEN CHIN-LONG , FIFIELD JOHN ATKINSON , KALTER HOWARD LEO
Abstract: In a memory system comprising a plurality of memory units (10) each of which possesses unit-level error correction capabilities (20) and each of which are tied to a system level error correction function (30), memory reliability is enhanced by providing means (Fig. 2) for disabling the unit-level error correction capability, for example, in response to the occurrence of an uncorrectable error in one of the memory units. This counter-intuitive approach which disables an error correction function nonetheless enhances overall memory system reliability since it enables the employment of the complement/recomplement algorithm which depends upon the presence of reproducible errors for proper operation. Thus, chip level error correction systems, which are increasingly desirable at high packaging densities, are employed in a way which does not interfere with system level error correction methods.
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公开(公告)号：DE69021413D1
公开(公告)日：1995-09-14
申请号：DE69021413
申请日：1990-02-02
Applicant: IBM
Inventor： BLAKE ROBERT MARTIN , BOSSEN DOUGLAS CRAIG , CHEN CHIN-LONG , FIFIELD JOHN ATKINSON , KALTER HOWARD LEO
Abstract: In a memory system comprising a plurality of memory units (10) each of which possesses unit-level error correction capabilities (20) and each of which are tied to a system level error correction function (30), memory reliability is enhanced by providing means (Fig. 2) for disabling the unit-level error correction capability, for example, in response to the occurrence of an uncorrectable error in one of the memory units. This counter-intuitive approach which disables an error correction function nonetheless enhances overall memory system reliability since it enables the employment of the complement/recomplement algorithm which depends upon the presence of reproducible errors for proper operation. Thus, chip level error correction systems, which are increasingly desirable at high packaging densities, are employed in a way which does not interfere with system level error correction methods.
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公开(公告)号：AU4939390A
公开(公告)日：1990-09-13
申请号：AU4939390
申请日：1990-02-09
Applicant: IBM
Inventor： BLAKE ROBERT MARTIN , BOSSEN DOUGLAS CRAIG , CHEN CHIN-LONG , FIFIELD JOHN ATKINSON , KALTER HOWARD LEO , LO TIN-CHEE
Abstract: In a memory system comprising a plurality of memory units (10) each of which possesses unit-level error correction capabilities (20) and each of which are tied to a system level error correction function (30), memory reliability is enhanced by providing means for fixing the output of one of the memory units at a fixed value in response to the occurrence of an uncorrectable error in one of the memory units. This counter-intuitive approach to the generation of forced hard errors nonetheless enhances overall memory system reliability since it enables the employment of the complement/recomplement algorithm which depends upon the presence of reproducible errors for proper operation. Thus, chip level error correction systems, which are increasingly desirable at high packaging densities, are employed in a way which does not interfere with system level error correction methods.
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Patent Agency Ranking
公开(公告)号：DE69026743D1
公开(公告)日：1996-06-05
申请号：DE69026743
申请日：1990-02-02
Applicant: IBM
Inventor： BLAKE ROBERT MARTIN , BOSSEN DOUGLAS CRAIG , CHEN CHIN-LONG , FIFIELD JOHN ATKINSON , KALTER HOWARD LEO , LO TIN-CHEE
Abstract: In a memory system comprising a plurality of memory units (10) each of which possesses unit-level error correction capabilities (20) and each of which are tied to a system level error correction function (30), memory reliability is enhanced by providing means for fixing the output of one of the memory units at a fixed value in response to the occurrence of an uncorrectable error in one of the memory units. This counter-intuitive approach to the generation of forced hard errors nonetheless enhances overall memory system reliability since it enables the employment of the complement/recomplement algorithm which depends upon the presence of reproducible errors for proper operation. Thus, chip level error correction systems, which are increasingly desirable at high packaging densities, are employed in a way which does not interfere with system level error correction methods.
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公开(公告)号：BR9001126A
公开(公告)日：1991-03-05
申请号：BR9001126
申请日：1990-03-09
Applicant: IBM
Inventor： BLAKE ROBERT MARTIN , BOSSEN DOUGLAS CRAIG , CHEN CHIN-LONG , FIFIELD JOHN ATKINSON , KALTER HOWARD LEO
Abstract: In a memory system comprising a plurality of memory units (10) each of which possesses unit-level error correction capabilities (20) and each of which are tied to a system level error correction function (30), memory reliability is enhanced by providing means (Fig. 2) for disabling the unit-level error correction capability, for example, in response to the occurrence of an uncorrectable error in one of the memory units. This counter-intuitive approach which disables an error correction function nonetheless enhances overall memory system reliability since it enables the employment of the complement/recomplement algorithm which depends upon the presence of reproducible errors for proper operation. Thus, chip level error correction systems, which are increasingly desirable at high packaging densities, are employed in a way which does not interfere with system level error correction methods.
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公开(公告)号：AU4939990A
公开(公告)日：1990-09-13
申请号：AU4939990
申请日：1990-02-09
Applicant: IBM
Inventor： BLAKE ROBERT MARTIN , BOSSEN DOUGLAS CRAIG , CHEN CHIN-LONG , FIFIELD JOHN ATKINSON , KALTER HOWARD LEO
Abstract: In a memory system comprising a plurality of memory units (10) each of which possesses unit-level error correction capabilities (20) and each of which are tied to a system level error correction function (30), memory reliability is enhanced by providing means (Fig. 2) for disabling the unit-level error correction capability, for example, in response to the occurrence of an uncorrectable error in one of the memory units. This counter-intuitive approach which disables an error correction function nonetheless enhances overall memory system reliability since it enables the employment of the complement/recomplement algorithm which depends upon the presence of reproducible errors for proper operation. Thus, chip level error correction systems, which are increasingly desirable at high packaging densities, are employed in a way which does not interfere with system level error correction methods.
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公开(公告)号：SG44390A1
公开(公告)日：1997-12-19
申请号：SG1996000087
申请日：1990-02-02
Applicant: IBM
Inventor： BLAKE ROBERT MARTIN , BOSSEN DOUGLAS CRAIG , CHEN CHIN-LONG , FIFIELD JOHN ATKINSON , KALTER HOWARD LEO , LO TIN-CHEE
Abstract: In a memory system comprising a plurality of memory units (10) each of which possesses unit-level error correction capabilities (20) and each of which are tied to a system level error correction function (30), memory reliability is enhanced by providing means for fixing the output of one of the memory units at a fixed value in response to the occurrence of an uncorrectable error in one of the memory units. This counter-intuitive approach to the generation of forced hard errors nonetheless enhances overall memory system reliability since it enables the employment of the complement/recomplement algorithm which depends upon the presence of reproducible errors for proper operation. Thus, chip level error correction systems, which are increasingly desirable at high packaging densities, are employed in a way which does not interfere with system level error correction methods.
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公开(公告)号：DE69026743T2
公开(公告)日：1996-11-07
申请号：DE69026743
申请日：1990-02-02
Applicant: IBM
Inventor： BLAKE ROBERT MARTIN , BOSSEN DOUGLAS CRAIG , CHEN CHIN-LONG , FIFIELD JOHN ATKINSON , KALTER HOWARD LEO , LO TIN-CHEE
Abstract: In a memory system comprising a plurality of memory units (10) each of which possesses unit-level error correction capabilities (20) and each of which are tied to a system level error correction function (30), memory reliability is enhanced by providing means for fixing the output of one of the memory units at a fixed value in response to the occurrence of an uncorrectable error in one of the memory units. This counter-intuitive approach to the generation of forced hard errors nonetheless enhances overall memory system reliability since it enables the employment of the complement/recomplement algorithm which depends upon the presence of reproducible errors for proper operation. Thus, chip level error correction systems, which are increasingly desirable at high packaging densities, are employed in a way which does not interfere with system level error correction methods.
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