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公开(公告)号：HUT57453A
公开(公告)日：1991-11-28
申请号：HU110091
申请日：1991-04-04
Applicant: IBM
Inventor： BLANER BARTHOLOMEW , VASSILIADIS STAMATIS , PHILLIPS JAMES EDWARD
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公开(公告)号：PL289721A1
公开(公告)日：1991-10-07
申请号：PL28972191
申请日：1991-04-03
Applicant: IBM
Inventor： BLANER BARTHOLOMEW , VASSILIADIS STAMATIS , PHILLIPS JAMES EDWARD
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公开(公告)号：DE69132271T2
公开(公告)日：2000-12-21
申请号：DE69132271
申请日：1991-03-29
Applicant: IBM
Inventor： VASSILIADIS STAMATIS , BLANER BARTHOLOMEW , JEREMIAH LEO
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公开(公告)号：DE69131956T2
公开(公告)日：2000-07-20
申请号：DE69131956
申请日：1991-04-03
Applicant: IBM
Inventor： VASSILIADIS STAMATIS , BLANER BARTHOLOMEW
Abstract: A digital computer system is described capable of processing two or more computer instructions in parallel and having a cache storage unit for temporarily storing machine-level computer instructions in their journey from a higher-level storage unit of the computer system to the functional units which process the instructions. The computer system includes an instruction compounding unit located intermediate to the higher-level storage unit and the cache storage unit for analyzing the instructions and generating for to each instruction a compounding information which indicates whether or not that instruction may be processed in parallel with one or more neighboring instructions in the instruction stream. These tagged instructions are then stored in the cache unit with the compounding information. The computer system further includes a plurality of functional instruction processing units which operate in parallel with one another. The instructions supplied to these functional units are obtained from the cache storage unit. At instruction issue time, the compounding information for the instructions is examined and those instructions indicated for parallel processing are sent to different ones of the functional units in accordance with the codings of their operation code fields.
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公开(公告)号：HU216990B
公开(公告)日：1999-10-28
申请号：HU2492
申请日：1991-03-29
Applicant: IBM
Inventor： BLANER BARTHOLOMEW , JEREMIAH THOMAS LEO , VASSILIADIS STAMATIS
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Patent Agency Ranking
公开(公告)号：AT146611T
公开(公告)日：1997-01-15
申请号：AT91104323
申请日：1991-03-20
Applicant: IBM
Inventor： BLANER BARTHOLOMEW , VASSILIADIS STAMATIS
Abstract: Described is a scalable compound instruction set machine and method which provides for processing a set of instructions or program to be executed by a computer to determine statically which instructions may be combined into compound instructions which are executed in parallel by a scalar machine. Such processing looks for classes of instructions that can be executed in parallel without data-dependent or hardware-dependent interlocks. Without regard to their original sequence the individual instructions are combined with one or more other individual instructions to form a compound instruction which eliminates interlocks. Control information is appended to identify information relevant to the execution of the compound instructions. The result is a stream of scalar instructions compounded or grouped together before instruction decode time so that they are already flagged and identified for selective simultaneous parallel execution by execution units. The compounding does not change the object code results and existing programs realize performance improvements while maintaining compatibility with previously implemented systems for which the original set of instructions was provided.
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公开(公告)号：SK93491A3
公开(公告)日：1995-09-13
申请号：SK93491
申请日：1991-04-04
Applicant: IBM
Inventor： BLANER BARTHOLOMEW , VASSILIADIS STAMATIS , EICHEMEYER RICHARD J
Abstract: A digital computer system is described capable of processing two or more computer instructions in parallel and having a main memory unit for storing information blocks including the computer instructions includes an instruction compounding unit for analyzing the instructions and adding to each instruction a tag field which indicates whether or not that instruction may be processed in parallel with another neighboring instruction. Tagged instructions are stored in the main memory. The computer system further includes a plurality of functional instruction processing units which operate in parallel with one another. The instructions supplied to the functional units are obtained from the memory by way of a cache storage unit. At instruction issue time, the tag fields of the instructions are examined and those tagged for parallel processing are sent to different ones of the functional units in accordance with the codings of their operation code fields.
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公开(公告)号：CA2040304C
公开(公告)日：1995-04-11
申请号：CA2040304
申请日：1991-04-12
Applicant: IBM
Inventor： BLANER BARTHOLOMEW , VASSILIADIS STAMATIS
Abstract: A digital computer system capable of processing two or more computer instructions in parallel and having a cache storage unit for temporarily storing machine-level computer instructions in their journey from a higher-level storage unit of the computer system to the functional units which process the instructions. The computer system includes an instruction compounding unit located intermediate to the higher-level storage unit and the cache storage unit for analyzing the instructions and adding to each instruction a tag field which indicates whether or not that instruction may be processed in parallel with one or more neighboring instructions in the instruction stream. These tagged instructions are then stored in the cache unit. The computer system further includes a plurality of functional instruction processing units which operate in parallel with one another. The instructions supplied to these functional units are obtained from the cache storage unit. At instruction issue time, the tag fields of the instructions are examined and those tagged for parallel processing are sent to different ones of the functional units in accordance with the codings of their operation code fields.
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公开(公告)号：CA2039639C
公开(公告)日：1995-02-14
申请号：CA2039639
申请日：1991-04-03
Applicant: IBM
Inventor： VASSILIADIS STAMATIS , PHILLIPS JAMES E , BLANER BARTHOLOMEW
Abstract: A multi-function ALU for use in digital data processing is described, which facilitates the execution of instructions in parallel, thereby increasing processor performance. The proposed apparatus reduces the instruction execution latency that results from data dependency hazards in a pipelined machine. This latency reduction is accomplished by collapsing the interlocks due to these hazards. The proposed apparatus achieves performance improvement while maintaining compatibility with previous implementations designed using an identical architecture.
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公开(公告)号：BR9101791A
公开(公告)日：1992-04-28
申请号：BR9101791
申请日：1991-05-03
Applicant: IBM
Inventor： BLANER BARTHOLOMEW , VASSILIADIS STAMATIS
Abstract: A digital computer system is described capable of processing two or more computer instructions in parallel and having a cache storage unit for temporarily storing machine-level computer instructions in their journey from a higher-level storage unit of the computer system to the functional units which process the instructions. The computer system includes an instruction compounding unit located intermediate to the higher-level storage unit and the cache storage unit for analyzing the instructions and generating for to each instruction a compounding information which indicates whether or not that instruction may be processed in parallel with one or more neighboring instructions in the instruction stream. These tagged instructions are then stored in the cache unit with the compounding information. The computer system further includes a plurality of functional instruction processing units which operate in parallel with one another. The instructions supplied to these functional units are obtained from the cache storage unit. At instruction issue time, the compounding information for the instructions is examined and those instructions indicated for parallel processing are sent to different ones of the functional units in accordance with the codings of their operation code fields.
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