公开(公告)号：WO2004109776A3

公开(公告)日：2005-05-19

申请号：PCT/US2004016903

申请日：2004-05-28

Applicant: IBM ,  BEDELL STEPHEN W ,  CHEN HUAJIE ,  FOGEL KEITH E ,  SADANA DEVENDRA K

Inventor： BEDELL STEPHEN W ,  CHEN HUAJIE ,  FOGEL KEITH E ,  SADANA DEVENDRA K

IPC: H01L21/20 ,  H01L21/762 ,  H01L21/306

CPC classification number: H01L21/7624 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/02664 ,  Y10T428/12674

Abstract: The present invention provides a method of fabricating a SiGe-on-insulator substrate in which lattice engineering is employed to decouple the interdependence between SiGe thickness, Ge fraction and strain relaxation. The method includes providing a SiGe-on-insulator substrate material comprising a SiGe alloy layer having a selected in-plane lattice parameter, a selected thickness parameter and a selected Ge content parameter, wherein the selected in-plane lattice parameter has a constant value and one or both of the other parameters, i.e., thickness or Ge content, have adjustable values; and adjusting one or both of the other parameters to final selected values, while maintaining the selected in-plane lattice parameter. The adjusting is achieved utilizing either a thinning process or a thermal dilution process depending on which parameters are fixed and which are adjustable.

Abstract translation: 本发明提供了一种制造绝缘体上硅衬底的方法，其中使用晶格工程来去耦合SiGe厚度，Ge分数和应变松弛之间的相互依赖性。 该方法包括提供一种绝缘体上硅衬底材料，其包括具有选定的面内晶格参数的SiGe合金层，选定的厚度参数和所选择的Ge含量参数，其中所选择的面内晶格参数具有恒定值， 一个或两个其他参数，即厚度或Ge含量，具有可调整的值; 并且在保持所选择的平面内晶格参数的同时将其他参数中的一个或两个调整为最终选择的值。 根据哪些参数是固定的，哪些是可调节的，利用稀化过程或热稀释过程实现调节。

公开(公告)号：JP2005026681A

公开(公告)日：2005-01-27

申请号：JP2004183839

申请日：2004-06-22

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： BEDELL STEPHEN W ,  CHEN HUAJIE ,  DOMENICUCCI ANTHONY G ,  FOGEL KEITH E ,  SADANA DEVENDRA K

IPC: H01L27/12 ,  H01L21/02 ,  H01L21/20 ,  H01L21/762

CPC classification number: H01L21/7624 ,  Y10S438/933 ,  Y10T428/12674

Abstract: PROBLEM TO BE SOLVED: To provide a method for manufacturing an SiGe-on-insulator substrate material substantially relaxed, of high quality, and capable of being used as a template for strained-silicon. SOLUTION: The SOI substrate having an ultra-thin top Si layer is used as the template for compressive strain SiGe growth. When an SiGe layer is relaxed at an enough temperature, the property of its dislocation movement is such that strain release defect moves down into the thin Si layer when an embedded oxide shows semi-viscosity behavior. The thin Si layer is consumed by oxidation of an interface of the thin Si with the embedded oxide. This can be performed by using inner oxidation at a high temperature. Therefore, the role of the original thin Si layer is to use the inner oxidation and subsequently to act as a sacrificial defective sink capable of being consumed during an SiGe alloy being relaxed. COPYRIGHT: (C)2005,JPO&NCIPI

Abstract translation: 要解决的问题：提供一种制造绝缘体上绝缘体衬底材料的方法，其基本上是松弛的，高质量的，并且能够用作应变硅的模板。 解决方案：使用具有超薄顶部Si层的SOI衬底作为压缩应变SiGe生长的模板。 当SiGe层在足够的温度下松弛时，其位错运动的性质使得当嵌入的氧化物显示半粘度行为时，应变释放缺陷向下移动到薄的Si层中。 薄的Si层被薄的Si与嵌入的氧化物的界面的氧化所消耗。 这可以通过在高温下使用内部氧化来进行。 因此，原始薄Si层的作用是使用内部氧化，随后作为在SiGe合金松弛期间能够消耗的牺牲缺陷槽。 版权所有（C）2005，JPO＆NCIPI

公开(公告)号：JP2004319983A

公开(公告)日：2004-11-11

申请号：JP2004085745

申请日：2004-03-23

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： CHEN HUAJIE ,  SUBBANNA SESHADRI ,  JAGANNATHAN BASANTH ,  GREGORY G FREEMAN ,  AHLGREN DAVID C ,  ANGELL DAVID ,  SCHONENBERG KATHRYN T ,  STEIN KENNETH J ,  JAMIN FEN F

IPC: H01L21/331 ,  H01L21/8249 ,  H01L27/06 ,  H01L29/732 ,  H01L29/737 ,  H01L29/78

CPC classification number: H01L21/8249 ,  H01L27/0623

Abstract: PROBLEM TO BE SOLVED: To provide a method for forming a BiCMOS integrated circuit having a raised external base.
SOLUTION: This method comprises a step for forming a polycrystal silicon layer on the surface of a gate dielectric substance 18 provided on a substrate having a device section 14 in which a bipolar transistor is formed and a device section 16 in which a CMOS transistor is formed. Then, the polycrystal silicon layer is patterned, and a sacrifice polycrystal silicon layer is formed above the device section in which the bipolar transistor is formed and the section around it. Meanwhile, a gate conductor is provided in the device section in which the CMOS transistor is formed at the same time. Then, a spacer 30 is provided around each of the gate conductor. Then a part of the sacrifice polycrystal silicon layer on the bipolar device section is selectively removed to provide an opening in the device section in which the bipolar transistor is formed. Then the bipolar transistor having a raised external base 58 is formed at the opening.
COPYRIGHT: (C)2005,JPO&NCIPI

Abstract translation: 要解决的问题：提供一种用于形成具有凸起的外部基底的BiCMOS集成电路的方法。 解决方案：该方法包括在设置在其上形成有双极晶体管的器件部分14的衬底上的栅极电介质18的表面上形成多晶硅层的步骤，以及器件部分16，其中CMOS 形成晶体管。 然后，对多晶硅层进行构图，在形成双极型晶体管的器件部分上方形成牺牲多晶硅层，并在其周围形成截面。 同时，在同时形成CMOS晶体管的器件部分中提供栅极导体。 然后，围绕每个栅极导体设置间隔件30。 然后，选择性地去除双极器件部分上牺牲多晶硅层的一部分，以在其中形成双极晶体管的器件部分中提供开口。 然后在开口处形成具有升高的外部基座58的双极晶体管。 版权所有（C）2005，JPO＆NCIPI

公开(公告)号：JP2005079601A

公开(公告)日：2005-03-24

申请号：JP2004256027

申请日：2004-09-02

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： BEDELL STEPHEN W ,  CHEN HUAJIE ,  FOGEL KEITH E ,  SADANA DEVENDRA K

IPC: H01L29/161 ,  C30B29/52 ,  C30B31/02 ,  H01L21/02 ,  H01L21/20 ,  H01L21/205 ,  H01L21/762 ,  H01L21/8238 ,  H01L27/12 ,  H01L29/04

CPC classification number: H01L21/7624 ,  C30B29/52 ,  C30B31/02 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/02694 ,  Y10T428/24917

Abstract: PROBLEM TO BE SOLVED: To provide a manufacturing method for making a metastable strained SiGe layer. SOLUTION: The metastable SiGe layer is made by the method which includes a process that a layer containing Ge is formed on a surface of a layer disposed on a barrier layer to Ge diffusion containing Si in its upper surface portion thickness of 500 Å or less, and a process that a substantially metastable SiGe layer showing relaxation resistive property on the barrier layer is formed by heating the above-mentioned respective layers at the temperature enabling Ge to diffuse through the layer containing Si in its upper surface portion and the layer containing Ge mutually. COPYRIGHT: (C)2005,JPO&NCIPI

Abstract translation: 要解决的问题：提供一种制造亚稳态应变SiGe层的制造方法。 解决方案：亚稳态SiGe层是通过以下方法制成的，该方法包括：在设置在阻挡层上的层的表面上形成含有Ge的层，其上表面部分厚度为含有Si的Ge扩散 并且通过在使Ge能够通过其上表面部分中含有Si的层扩散的温度下加热上述各层来形成在阻挡层上显示松弛电阻性质的基本上亚稳态的SiGe层的工艺， 包含Ge相互。 版权所有（C）2005，JPO＆NCIPI

公开(公告)号：JP2004221582A

公开(公告)日：2004-08-05

申请号：JP2004003465

申请日：2004-01-08

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： CHEN HUAJIE ,  SCHONENBERG KATHRYN T ,  GREGORY G FREEMAN ,  STRICKER ANDREAS D ,  RIEH JAE-SUNG

IPC: H01L21/321 ,  H01L21/331 ,  H01L29/732 ,  H01L29/737

CPC classification number: H01L29/66242 ,  H01L21/32105 ,  Y10S438/911

Abstract: PROBLEM TO BE SOLVED: To provide a self-aligning oxide mask formed by utilizing the difference in oxidation speed between different materials.
SOLUTION: The self-aligning oxide mask is formed on a CVD growth base NPN base layer including a single crystal Si52 (Si/SiGe) in an active area and a poly-crystal Si51 (Si/SiGe). The self-aligning mask is fabricated by utilizing the fact that the poly-crystal Si (Si/SiGe) oxidizes faster than the single crystal Si (Si/SiGe). By using the thermal oxidation method, a thick oxide layer is formed on the poly-crystal Si (Si/SiGe) and a thin oxide layer is formed on the single crystal Si (Si/SiGe), thereby the oxide films are formed on both the poly-crystal Si (Si/SiGe) and the single crystal Si (Si/SiGe), and by the control of etching of the oxide, the thin oxide layer on the single crystal Si (Si/SiGe) is removed while the self-alignment oxide mask layer is left on the poly-crystal Si (Si/SiGe).
COPYRIGHT: (C)2004,JPO&NCIPI

公开(公告)号：WO2005027192A3

公开(公告)日：2006-12-21

申请号：PCT/US2004028163

申请日：2004-08-30

Applicant: IBM ,  DOKUMACI OMER ,  CHEN HUAJIE ,  CHIDAMBARRAO DURESETI ,  YANG HAINING S

Inventor： DOKUMACI OMER ,  CHEN HUAJIE ,  CHIDAMBARRAO DURESETI ,  YANG HAINING S

IPC: H01L29/73 ,  H01L21/265 ,  H01L21/336 ,  H01L21/8238 ,  H01L29/78

CPC classification number: H01L29/6653 ,  H01L21/26586 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823835 ,  H01L21/823864 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/7833 ,  H01L29/7848

Abstract: A structure and method are provided in which an n-type field effect transistor (NFET) and a p-type field effect transistor (PFET) each have a channel region disposed in a single-crystal layer of a first semiconductor and a stress is applied at a first magnitude to a channel region of the PFET but not at that magnitude to the channel region of the NFET. The stress is applied by a layer of a second semiconductor which is lattice-mismatched to the first semiconductor. The layer of second semiconductor is formed over the source and drain regions and extensions of the PFET at a first distance from the channel region of the PFET and is formed over the source and drain regions of the NFET at a second, greater distance from the channel region of the NFET, or not formed at all in the NFET.

Abstract translation: 提供了一种结构和方法，其中n型场效应晶体管（NFET）和p型场效应晶体管（PFET）各自具有设置在第一半导体的单晶层中的沟道区域并施加应力 在第一幅度上与PFET的沟道区不同，但与NFET的沟道区不同。 应力由第一半导体晶格失配的第二半导体层施加。 第二半导体层形成在PFET的源极和漏极区域以及与PFET的沟道区第一距离处的延伸部分之间，并且形成在NFET的源极和漏极区域之上，距离沟道的第二更远的距离 NFET的区域，或者根本不形成在NFET中。

公开(公告)号：AT504078T

公开(公告)日：2011-04-15

申请号：AT04780054

申请日：2004-08-04

Applicant: IBM

Inventor： CHEN HUAJIE ,  CHIDAMBARRAO DURESETI ,  GLUSCHENKOV OLEG G ,  STEEGEN AN ,  YANG HAINING

IPC: H01L21/336 ,  H01L21/20 ,  H01L21/8238 ,  H01L21/84 ,  H01L27/092 ,  H01L27/12

Abstract: A process is provided for making a PFET and an NFET. Areas in a first semiconductor region adjacent to a gate stack are recessed. A lattice-mismatched semiconductor layer is grown in the recesses to apply a strain to the channel region of the PFET adjacent thereto. A layer of the first semiconductor material can be grown over the lattice-mismatched semiconductor layer and a salicide formed from the layer of silicon to provide low-resistance source and drain regions.

公开(公告)号：WO2005043591A3

公开(公告)日：2007-06-21

申请号：PCT/US2004034562

申请日：2004-10-19

Applicant: IBM ,  CHIDAMBARRAO DURESETI ,  DOKUMACI OMER ,  CHEN HUAJIE

Inventor： CHIDAMBARRAO DURESETI ,  DOKUMACI OMER ,  CHEN HUAJIE

IPC: H01L21/00 ,  H01L20060101 ,  H01L21/336 ,  H01L21/461 ,  H01L21/8238 ,  H01L21/84 ,  H01L23/48 ,  H01L27/01 ,  H01L27/12 ,  H01L29/10 ,  H01L31/117

CPC classification number: H01L29/7848 ,  H01L21/3081 ,  H01L21/823807 ,  H01L21/823814 ,  H01L27/092 ,  H01L29/1054 ,  H01L29/66628 ,  H01L29/66636 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device and method of manufacturing a semiconductor device. The semiconductor device includes channels for a pFET and an nFET. A SiGe layer is selectively grown in the source and drain regions of the pFET channel and a Si:C layer is selectively grown in source and drain regions of the nFET channel. The SiGe and Si:C layer match a lattice network of the underlying Si layer to create a stress component. In one implementation, this causes a compressive component in the pFET channel and a tensile component in the nFET channel.

Abstract translation: 半导体器件及半导体器件的制造方法。 半导体器件包括用于pFET和nFET的沟道。 在pFET沟道的源极和漏极区域选择性地生长SiGe层，并且在nFET沟道的源极和漏极区域选择性地生长Si：C层。 SiGe和Si：C层与下层Si层的晶格网络匹配以产生应力分量。 在一个实现中，这导致pFET沟道中的压缩分量和nFET沟道中的拉伸分量。

公开(公告)号：WO2005017964A2

公开(公告)日：2005-02-24

申请号：PCT/US2004025152

申请日：2004-08-04

Applicant: IBM ,  CHEN HUAJIE ,  CHIDAMBARRAO DURESETI ,  GLUSCHENKOV OLEG G ,  STEEGEN AN L ,  YANG HAINING S

Inventor： CHEN HUAJIE ,  CHIDAMBARRAO DURESETI ,  GLUSCHENKOV OLEG G ,  STEEGEN AN L ,  YANG HAINING S

IPC: H01L21/20 ,  H01L21/336 ,  H01L21/8238 ,  H01L21/84 ,  H01L27/092 ,  H01L27/12 ,  H01L

CPC classification number: H01L21/84 ,  H01L21/02532 ,  H01L21/02636 ,  H01L21/823807 ,  H01L21/823814 ,  H01L27/0922 ,  H01L27/1203 ,  H01L29/165 ,  H01L29/6656 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7848

Abstract: A p-type field effect transistor (PFET) and an n-type field effect transistor (NFET) of an integrated circuit are provided. A first strain is applied to the channel region of the PFET but not the NFET via a lattice-mismatched semiconductor layer such as silicon germanium disposed in source and drain regions of only the PFET and not of the NFET. A process of making the PFET and NFET is provided. Trenches are etched in the areas to become the source and drain regions of the PFET and a lattice-mismatched silicon germanium layer is grown epitaxially therein to apply a strain to the channel region of the PFET adjacent thereto. A layer of silicon can be grown over the silicon germanium layer and a salicide formed from the layer of silicon to provide low-resistance source and drain regions.

Abstract translation: 提供集成电路的p型场效应晶体管（PFET）和n型场效应晶体管（NFET）。 第一应变施加到PFET的沟道区，而不是NFET通过位于仅仅PFET而不是NFET的源极和漏极区域中的晶格不匹配的半导体层，例如硅锗。 提供制造PFET和NFET的工艺。 在区域中蚀刻沟槽以成为PFET的源极和漏极区域，并且将晶格失配的硅锗层外延生长以向与其相邻的PFET的沟道区域施加应变。 可以在硅锗层上生长一层硅层，并从硅层形成硅化物以提供低电阻源极和漏极区域。

公开(公告)号：WO2006017640B1

公开(公告)日：2006-04-27

申请号：PCT/US2005027691

申请日：2005-08-04

Applicant: IBM ,  BEDELL STEPHEN W ,  CHEN HUAJIE ,  FOGEL KEITH ,  MITCHELL RYAN M ,  SADANA DEVENDRA K

Inventor： BEDELL STEPHEN W ,  CHEN HUAJIE ,  FOGEL KEITH ,  MITCHELL RYAN M ,  SADANA DEVENDRA K

IPC: H01L21/36 ,  H01L21/20 ,  H01L31/117

CPC classification number: H01L29/1054 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02507 ,  H01L21/02532

Abstract: A method is disclosed for forming a strained Si layer on SiGe, where the SiGe layer has improved thermal conductivity. A first layer (41) of Si or Ge is deposited on a substrate (10) in a first depositing step; a second layer (42) of the other element is deposited on the first layer in a second depositing step; and the first and second depositing steps are repeated so as to form a combined SiGe layer (50) having a plurality of Si layers and a plurality of Ge layers (41-44). The respective thicknesses of the Si layers and Ge layers are in accordance with a desired composition ratio of the combined SiGe layer. The combined SiGe layer (50) is characterized as a digital alloy of Si and Ge having a thermal conductivity greater than that of a random alloy of Si and Ge. This method may further include the step of depositing a Si layer (61) on the combined SiGe layer (50); the combined SiGe layer is characterized as a relaxed SiGe layer, and the Si layer (61) is a strained Si layer. For still greater thermal conductivity in the SiGe layer, the first layer and second layer may be deposited so that each layer consists essentially of a single isotope.

Abstract translation: 公开了一种在SiGe上形成应变Si层的方法，其中SiGe层具有改善的导热性。 在第一沉积步骤中，在衬底（10）上沉积Si或Ge的第一层（41） 在第二沉积步骤中将另一元素的第二层（42）沉积在第一层上; 并重复第一沉积步骤和第二沉积步骤以形成具有多个Si层和多个Ge层（41-44）的组合SiGe层（50）。 Si层和Ge层的各自厚度符合组合SiGe层的所需组成比。 组合的SiGe层（50）的特征在于Si和Ge的数字合金，其导热率大于Si和Ge的无规合金的导热率。 该方法可以进一步包括在组合的SiGe层（50）上沉积Si层（61）的步骤; 组合的SiGe层的特征在于弛豫SiGe层，并且Si层（61）是应变Si层。 为了在SiGe层中具有更大的导热性，可以沉积第一层和第二层，使得每个层基本上由单一的同位素组成。