公开(公告)号：EP1692717A4

公开(公告)日：2008-04-09

申请号：EP03819249

申请日：2003-12-08

Applicant: IBM

Inventor： BUEHRER FREDERICK WILLIAM ,  CHIDAMBARRAO DURESETI ,  DORIS BRUCE B ,  HUANG HSIANG-JEN ,  YANG HAINING

IPC: H01L21/336 ,  H01L21/22 ,  H01L21/265 ,  H01L21/324 ,  H01L21/425 ,  H01L21/8238 ,  H01L27/01 ,  H01L29/10 ,  H01L29/167 ,  H01L29/76

CPC classification number: H01L29/7842 ,  H01L21/22 ,  H01L21/26513 ,  H01L21/26586 ,  H01L21/324 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/1083 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7843

Abstract: A stressed film applied across a boundary defined by a structure or a body (e.g. substrate or layer ) of semiconductor material provides a change from tensile to compressive stress in the semiconductor material proximate to the boundary and is used to modify boron diffusion rate during annealing and thus modify final boron concentrations and/or profiles/gradients. In the case of a field effect transistor, the gate structure may be formed with or without sidewalls to regulate the location of the boundary relative to source/drain, extension and/or halo implants. Different boron diffusion rates can be produced in the lateral and vertical directions and diffusion rates comparable to arsenic can be achieved. Reduction of junction capacitance of both nFETs and pFETs can be achieved simultaneously with the same process steps.

Abstract translation: 施加在由半导体材料的结构或主体（例如衬底或层）限定的边界上的应力膜提供了在接近边界的半导体材料中从拉应力至压应力的变化，并且用于修改退火期间的硼扩散速率和 从而改变最终的硼浓度和/或分布/梯度。 在场效应晶体管的情况下，栅极结构可以形成为具有或不具有侧壁以相对于源极/漏极，延伸和/或晕圈注入来调节边界的位置。 可以在横向和垂直方向上产生不同的硼扩散速率，并且可以实现与砷相当的扩散速率。 可以通过相同的工艺步骤同时实现nFET和pFET的结电容的降低。

公开(公告)号：EP2089909A4

公开(公告)日：2009-12-23

申请号：EP07844145

申请日：2007-10-11

Applicant: IBM

Inventor： LI WAI-KIN ,  YANG HAINING

IPC: H01L21/28 ,  H01L21/336 ,  H01L29/423 ,  H01L29/49 ,  H01L29/78

CPC classification number: H01L29/42316 ,  H01L21/28097 ,  H01L21/28518 ,  H01L29/4975 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/78 ,  Y10S977/892

公开(公告)号：EP1834350A4

公开(公告)日：2009-06-17

申请号：EP05853245

申请日：2005-12-08

Applicant: IBM

Inventor： CHIDAMBARRAO DURESETI ,  LI YING ,  MALIK RAJEEV ,  NARASIMHA SHREESH ,  YANG HAINING ,  ZHU HUILONG

IPC: H01L21/336 ,  H01L29/78

CPC classification number: H01L29/7843 ,  H01L21/823807 ,  H01L29/66772 ,  Y10S438/938

Abstract: The present invention provides a semiconductor device having dual nitride liners, which provide an increased transverse stress state for at least one FET (300) and methods for the manufacture of such a device. A first aspect of the invention provides a method for use in the manufacture of a semiconductor device comprising the steps of applying a first silicon nitride liner (360) to the device and applying a second silicon nitride liner (370) adjacent the fast silicon nitride liner, wherein at least one of the first and second silicon nitride liners induces a transverse stress in a silicon channel (330) beneath at least one of the first and second silicon nitride liner.

公开(公告)号：EP2084711A4

公开(公告)日：2009-11-25

申请号：EP07843111

申请日：2007-09-25

Applicant: IBM

Inventor： YANG CHIH-CHAO ,  YANG HAINING

IPC: G11C17/14 ,  H01L23/525

CPC classification number: H01L23/5256 ,  H01L2924/0002 ,  H01L2924/00

公开(公告)号：WO2004053979A8

公开(公告)日：2005-05-12

申请号：PCT/EP0350957

申请日：2003-12-08

Applicant: IBM ,  IBM DEUTSCHLAND ,  INFINEON TECHNOLOGIES AG

Inventor： CLEVENGER LARRY ,  DALTON TIMOTHY ,  HOINKIS MARK ,  KALDOR STEFFEN ,  KUMAR KAUSHIK ,  LA TULIPE DOUGLAS JR ,  SEO SOON-CHEON ,  SIMON ANDREW ,  WANG YUN-YU ,  YANG CHIH-CHAO ,  YANG HAINING

IPC: H01L21/768

CPC classification number: H01L21/76843 ,  H01L21/76805 ,  H01L21/76807 ,  H01L21/76834 ,  H01L21/76835 ,  H01L21/76844 ,  H01L21/76847 ,  H01L21/76865

Abstract: Disclosed is a method for depositing a metal layer on an interconnect structure for a semiconductor wafer. In the method, a metal conductor (14) is covered by a capping layer (16) and a dielectric layer (18). The dielectric layer is patterned so as to expose the capping layer. The capping layer is then sputter etched to remove the capping layer and expose the metal conductor (14). In the process of sputter etching, the capping layer is redeposited (22) onto the sidewall of the pattern. Lastly, at least one layer is deposited into the pattern and covers the redeposited capping layer.

Abstract translation: 公开了一种用于在半导体晶片的互连结构上沉积金属层的方法。 在该方法中，金属导体（14）被覆盖层（16）和电介质层（18）覆盖。 对电介质层进行图案化以使覆盖层露出。 然后溅射蚀刻覆盖层以去除覆盖层并暴露金属导体（14）。 在溅射蚀刻的过程中，将覆盖层再沉积（22）到图案的侧壁上。 最后，至少一层沉积到图案中并覆盖再沉积的覆盖层。

公开(公告)号：EP1946360A4

公开(公告)日：2009-11-11

申请号：EP06825392

申请日：2006-10-02

Applicant: IBM

Inventor： YANG HAINING

IPC: H01L21/336 ,  H01L21/265 ,  H01L29/76 ,  H01L29/78

CPC classification number: H01L21/823425 ,  H01L21/26586 ,  H01L21/823468 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66659 ,  H01L29/7835

公开(公告)号：JP2004040095A

公开(公告)日：2004-02-05

申请号：JP2003178790

申请日：2003-06-23

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： MANDELMAN JACK A ,  RAMACHANDORA DEIVAKARUNI ,  YANG HAINING

IPC: H01L21/8242 ,  H01L27/108

CPC classification number: H01L27/10876 ,  H01L27/10864 ,  H01L27/10888 ,  H01L27/10891

Abstract: PROBLEM TO BE SOLVED: To provide a DRAM array employing a small vertical transistor of bitline capacitance. SOLUTION: A DRAM array comprising DRAM cells employing the vertical transistor increases electrical reliability and reduces the bitline capacitance by the use of an asymmetric structure in connection between a wordline 310 and the transistor. Thereby, the DRAM array permits the use of wider connection between the wordline 310 and a transistor electrode. Also, the word line 310 is used as an etch stop to protect a transistor gate 205 during the patterning of the wordline 310. COPYRIGHT: (C)2004,JPO

公开(公告)号：JP2004274063A

公开(公告)日：2004-09-30

申请号：JP2004064681

申请日：2004-03-08

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： YANG HAINING ,  RAMACHANDRA DEIBAKARUNI

IPC: H01L27/10 ,  H01L21/334 ,  H01L21/8242 ,  H01L27/108

CPC classification number: H01L27/1087 ,  H01L27/10841 ,  H01L29/66181

Abstract: PROBLEM TO BE SOLVED: To provide a method of forming a single bit line contact on a vertical transistor of a DRAM/e-DRAM device using a line forming master mask.
SOLUTION: By forming a patterning mask on the device with the line forming master mask, the part of the top surface of a gate electrode 100 is exposed on the top surface of a substrate. A divot reaching in the gate electrode alongside with a side wall spacer 300 juxtaposed with a source region 130 is etched, and filled with a dielectric material. A word line WL having a silicon nitride cap 220 is formed to be contacted with a gate electrode 100. An etching resistant conformal liner 230 is formed, and an ILD layer and a glass layer are formed. A bit line contact mask is formed to be patterned with the line forming master mask. A via hole BCV is etched to be juxtaposed with the side wall spacer 300 and reach to the source region 130, and the bit line contact is formed.
COPYRIGHT: (C)2004,JPO&NCIPI

公开(公告)号：JP2012253371A

公开(公告)日：2012-12-20

申请号：JP2012169233

申请日：2012-07-31

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： YANG HAINING

IPC: H01L21/8234 ,  H01L21/265 ,  H01L21/336 ,  H01L27/088 ,  H01L29/78

CPC classification number: H01L21/823425 ,  H01L21/26586 ,  H01L21/823468 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66659 ,  H01L29/7835

Abstract: PROBLEM TO BE SOLVED: To enable fabrication of an FET device that maintains a low series resistance between the gate and the source of the device, while minimizing adverse consequences formed by excessive gate-to-drain overlap.SOLUTION: The method includes forming a spacer layer 132 over a pair of adjacently spaced gate structures 102 which are disposed over a semiconductor substrate and comprise offset spacers 114. The gate structures are spaced such that the spacer layer is formed at a first thickness in a region between the gate structures and at a second thickness elsewhere, the second thickness being greater than the first thickness. The method also includes etching the spacer layer so as to form asymmetric spacer structures 124a, b adjacently to the offset spacers of the pair of adjacently spaced gate structures. The asymmetric spacer structures are used in defining source and drain regions.

Abstract translation: 要解决的问题：为了制造在器件的栅极和源极之间保持低串联电阻的FET器件，同时最小化由过大的栅极到漏极重叠形成的不利后果。 解决方案：该方法包括在一对相邻隔开的栅极结构102上形成间隔层132，该栅极结构102设置在半导体衬底上并且包括偏置间隔物114.栅极结构间隔开，使得间隔层形成在第一 栅极结构之间的区域的厚度和其他地方的第二厚度，第二厚度大于第一厚度。 该方法还包括蚀刻间隔层以便形成与该对相邻间隔开的栅极结构中的偏移间隔物相邻的非对称间隔结构124a，b。 不对称间隔结构用于限定源区和漏区。 版权所有（C）2013，JPO＆INPIT

公开(公告)号：JP2007251163A

公开(公告)日：2007-09-27

申请号：JP2007057115

申请日：2007-03-07

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： DYER THOMAS W ,  YANG HAINING ,  LUO ZHIJIONG

IPC: H01L29/78 ,  H01L29/786

CPC classification number: H01L29/0653 ,  H01L21/76243 ,  H01L21/76267 ,  H01L21/76283 ,  H01L21/823481 ,  H01L21/823878 ,  H01L21/84 ,  H01L27/1203

Abstract: PROBLEM TO BE SOLVED: To provide a semiconductor-on-insulator (SOI) substrate which has a patterned buried insulator layer included in differing depths. SOLUTION: The SOI substrate has a substantially planar upper surface and further includes: (1) first regions that include no buried insulator in any way; (2) second regions that include first portions of a patterned buried insulator layer 12 at a first depth (i.e., a depth measured from the planar upper surface of the SOI substrate); and (3) third regions that include second portions of the patterned buried insulator layer 12 at a second depth, wherein the first depth is deeper than the second depth. One or more field effect transistors (FETs) 20, 40 can be formed in the SOI substrate. For example, the FETs may have: channel regions in the first regions of the SOI substrate; source regions and drain regions in the second regions of the SOI substrate; and source/drain extension regions in the third regions of the SOI substrate. COPYRIGHT: (C)2007,JPO&INPIT

Abstract translation: 要解决的问题：提供一种具有不同深度的图案化掩埋绝缘体层的绝缘体上半导体（SOI）衬底。 解决方案：SOI衬底具有基本平坦的上表面，并且还包括：（1）以任何方式不包括埋入绝缘体的第一区域; （2）在第一深度（即从SOI衬底的平面上表面测量的深度）上包括图案化的掩埋绝缘体层12的第一部分的第二区域; 和（3）第三区域，其包括在第二深度处的图案化掩埋绝缘体层12的第二部分，其中第一深度比第二深度深。 可以在SOI衬底中形成一个或多个场效应晶体管（FET）20,40。 例如，FET可以在SOI衬底的第一区域中具有：沟道区域; SOI衬底的第二区域中的源极区和漏极区; 以及SOI衬底的第三区域中的源极/漏极延伸区域。 版权所有（C）2007，JPO＆INPIT