公开(公告)号：WO03069658A2

公开(公告)日：2003-08-21

申请号：PCT/US0303352

申请日：2003-02-04

Applicant: IBM

Inventor： CHU JACK O ,  ISMAIL KHALED

IPC: H01L21/331 ,  H01L21/02 ,  H01L21/20 ,  H01L21/205 ,  H01L21/336 ,  H01L21/337 ,  H01L21/762 ,  H01L21/8238 ,  H01L27/08 ,  H01L27/092 ,  H01L27/12 ,  H01L29/161 ,  H01L29/165 ,  H01L29/73 ,  H01L29/78 ,  H01L29/786 ,  H01L27/00

CPC classification number: H01L29/78654 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02505 ,  H01L21/0251 ,  H01L21/02532 ,  H01L21/02664 ,  H01L21/76256 ,  H01L21/76259 ,  H01L29/66916 ,  H01L29/78603

Abstract: A method for fabricating a strained Si based layer, devices manufactured in this layer, and electronic systems comprising such layers and devices are disclosed. The method comprises the steps of growing epitaxially a SiGe layer on a substrate, and creating a varying Ge concentration in this SiGe layer. The Ge concentration in the SiGe layer includes a unique Ge overshoot zone, where the Ge concentration is abruptly and significantly increased. The Si based layer is epitaxially deposited onto the SiGe layer, whereby is becomes tensilely strained. It is also disclosed that the strained Si based layer, typically Si or SiGe, can be transferred to a different bulk substrate, or to an insulator.

Abstract translation: 公开了一种制造应变Si基层的方法，该层制造的器件，以及包括这些层和器件的电子系统。 该方法包括以下步骤：在衬底上外延生长SiGe层，并在该SiGe层中产生变化的Ge浓度。 SiGe层中的Ge浓度包括独特的Ge过冲区域，其中Ge浓度突然显着增加。 将Si基层外延沉积到SiGe层上，由此变得拉伸应变。 还公开了应变Si基层（通常为Si或SiGe）可以转移到不同的体基板或绝缘体。

公开(公告)号：WO2005083750A3

公开(公告)日：2005-10-27

申请号：PCT/US2005005570

申请日：2005-02-22

Applicant: IBM ,  CHU JACK O ,  DEHLINGER GABRIEL K ,  GRILL ALFRED ,  KOESTER STEVEN J ,  OUYANG QIGING ,  SCHAUB JEREMY D

Inventor： CHU JACK O ,  DEHLINGER GABRIEL K ,  GRILL ALFRED ,  KOESTER STEVEN J ,  OUYANG QIGING ,  SCHAUB JEREMY D

IPC: H01L31/101

CPC classification number: H01L31/101

Abstract: The invention addresses the problem of creating a high-speed, high-efficiency photodetector that is compatible with Si CMOS technology. The structure consists of a Ge absorbing layer on a thin SOI substrate, and utilizes isolation regions, alternating n-­and p-type contacts, and low-resistance surface electrodes. The device achieves high bandwidth by utilizing a buried insulating layer to isolate carriers generated in the underlying substrate, high quantum efficiency over a broad spectrum by utilizing a Ge absorbing layer, low voltage operation by utilizing thin a absorbing layer and narrow electrode spacings, and compatibility with CMOS devices by virtue of its planar structure and use of a group IV absorbing material. The method for fabricating the photodetector uses direct growth of Ge on thin SOI or an epitaxial oxide, and subsequent thermal annealing to achieve a high-quality absorbing layer. This method limits the amount of Si available for interdiffusion, thereby allowing the Ge layer to be annealed without causing substantial dilution of the Ge layer by the underlying Si.

Abstract translation: 本发明解决了创建与Si CMOS技术兼容的高速，高效率光电探测器的问题。 该结构由薄SOI衬底上的Ge吸收层组成，并利用隔离区，交替的n型和p型触点以及低电阻表面电极。 该器件利用掩埋绝缘层隔离底层衬底中产生的载流子，通过利用Ge吸收层在广谱上获得高量子效率，利用薄吸收层和窄电极间距实现低电压操作，以及兼容性 凭借其平面结构和使用IV族吸收材料而具有CMOS器件。 用于制造光电检测器的方法使用在薄SOI或外延氧化物上直接生长Ge，并且随后进行热退火以实现高质量的吸收层。 该方法限制了可用于相互扩散的Si的量，由此允许Ge层退火而不会导致Ge层基本上被下面的Si稀释。

公开(公告)号：WO2004047150A3

公开(公告)日：2004-06-24

申请号：PCT/US0336969

申请日：2003-11-19

Applicant: IBM ,  CHRISTIANSEN SILKE H ,  CHU JACK O ,  GRILL ALFRED ,  MOONEY PATRICIA M

Inventor： CHRISTIANSEN SILKE H ,  CHU JACK O ,  GRILL ALFRED ,  MOONEY PATRICIA M

IPC: H01L21/20 ,  H01L21/265 ,  H01L21/762 ,  H01L21/302 ,  H01L21/461

CPC classification number: H01L21/26506 ,  H01L21/02378 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/02664 ,  H01L21/02667 ,  H01L21/02694 ,  H01L21/7624 ,  H01L21/76251 ,  Y10S438/933

Abstract: A method to obtain thin (less than 300 nm) strain-relaxed Si1-xGex buffer layers on Si or silicon-on-insulator (SOI) substrates. These buffer layers have a homogeneous distribution of misfit dislocations that relieve the strain, remarkably smooth surfaces, and a low threading dislocation (TD) density, i.e. less than 10 cm . The approach begins with the growth of a pseudomorphic or nearlypseudomorphic Si1-xGex layer, i.e., a layer that is free of misfit dislocations, which is then implanted with He or other light elements and subsequently annealed to achieve the substantial strain relaxation. The very effective strain relaxation mechanism operatiing with this method is dislocation nucleation at He-inducedplatelets (not bubbles) that lie below the Si/Si1-xGex interface, parallel to the Si(001) surface.

Abstract translation: 在Si或绝缘体上硅（SOI）衬底上获得薄（小于300nm）应变弛豫Si1-xGex缓冲层的方法。 这些缓冲层具有失配位错的均匀分布，其缓解了应变，表面光滑平滑，以及低穿透位错（TD）密度，即小于10 6 cm 2。 该方法开始于伪晶体或近似假晶Si1-xGex层的生长，即，不具有失配位错的层，然后将其注入He或其它轻元素，随后退火以实现实质的应变弛豫。 用这种方法操作的非常有效的应变松弛机理是位于Si（001）表面Si / Si1-xGex界面以下的He诱导的电镀层（不是气泡）的位错成核。

公开(公告)号：AU2003208985A1

公开(公告)日：2003-09-04

申请号：AU2003208985

申请日：2003-02-04

Applicant: IBM

Inventor： CHU JACK O ,  ISMAIL KHALED

IPC: H01L21/331 ,  H01L21/02 ,  H01L21/20 ,  H01L21/205 ,  H01L21/336 ,  H01L21/337 ,  H01L21/762 ,  H01L21/8238 ,  H01L27/08 ,  H01L27/092 ,  H01L27/12 ,  H01L29/161 ,  H01L29/165 ,  H01L29/73 ,  H01L29/78 ,  H01L29/786 ,  H01L27/00

Abstract: A method for fabricating a strained Si based layer, devices manufactured in this layer, and electronic systems comprising such layers and devices are disclosed. The method comprises the steps of growing epitaxially a SiGe layer on a substrate, and creating a varying Ge concentration in this SiGe layer. The Ge concentration in the SiGe layer includes a unique Ge overshoot zone, where the Ge concentration is abruptly and significantly increased. The Si based layer is epitaxially deposited onto the SiGe layer, whereby is becomes tensilely strained. It is also disclosed that the strained Si based layer, typically Si or SiGe, can be transferred to a different bulk substrate, or to an insulator.

公开(公告)号：WO2006031247A3

公开(公告)日：2006-10-12

申请号：PCT/US2005008493

申请日：2005-03-15

Applicant: IBM ,  CHU JACK O ,  COBB MICHAEL A ,  SAUNDERS PHILIP A ,  SHI LEATHEN

Inventor： CHU JACK O ,  COBB MICHAEL A ,  SAUNDERS PHILIP A ,  SHI LEATHEN

IPC: H01L21/20 ,  H01L21/30 ,  H01L21/331 ,  H01L27/01 ,  H01L27/108 ,  H01L29/04 ,  H01L31/117

CPC classification number: H01L21/76254 ,  H01L21/0245 ,  H01L21/0251 ,  H01L29/1054

Abstract: A method for achieving a substantially defect free SGOI substrate which includes a SiGe layer that has a high Ge content of greater than about 25% atomic using a low temperature wafer bonding technique is described. The wafer bonding process described in the present application includes an initial prebonding annealing step that is capable of forming a bonding interface comprising elements of Si, Ge and O, i.e., interfacial SiGeO layer, between a SiGe layer and a low temperature oxide layer. The present invention also provides the SGOI substrate and structure that contains the same

Abstract translation: 描述了使用低温晶片键合技术实现包括具有高于约25％原子的高Ge含量的SiGe层的基本上无缺陷的SGOI衬底的方法。 本申请中描述的晶片键合工艺包括初始预键合退火步骤，其能够在SiGe层和低温氧化物层之间形成包括Si，Ge和O的元素（即，界面SiGeO层）的键合界面。 本发明还提供了包含SGOI基材和SGOI基材的结构

公开(公告)号：WO2005036613A3

公开(公告)日：2005-07-07

申请号：PCT/US2004028045

申请日：2004-08-27

Applicant: IBM ,  CHU JACK O ,  OUYANG QIQING C

Inventor： CHU JACK O ,  OUYANG QIQING C

IPC: H01L21/335 ,  H01L29/10 ,  H01L29/778 ,  H01L29/786

CPC classification number: H01L29/1054 ,  H01L29/78687

Abstract: A silicon and silicon germanium based semiconductor MODFET device design and method of manufacture. The MODFET design includes a high-mobility layer structure capable of ultra high-speed, low-noise for a variety of communication applications including RF, microwave, sub-millimeter-wave and millimeter-wave. The epitaxial field effect transistor layer structure includes critical (vertical and lateral) device scaling and layer structure design for a high mobility strained n-channel and p-channel transistor incorporating silicon and silicon germanium layers to form the optimum modulation-doped heterostructure on an ultra thin SOI or SGOI substrate capable of achieving greatly improved RF performance.

Abstract translation: 基于硅和硅锗的半导体MODFET器件设计和制造方法。 MODFET设计包括高迁移率层结构，能够为包括RF，微波，亚毫米波和毫米波在内的各种通信应用提供超高速，低噪声。 外延场效应晶体管层结构包括用于高迁移率应变n沟道和p沟道晶体管的临界（垂直和横向）器件缩放和层结构设计，所述高迁移率应变n沟道和p沟道晶体管结合硅和硅锗层以在超薄膜上形成最优调制掺杂异质结构 薄SOI或SGOI衬底能够实现极大改进的射频性能。

公开(公告)号：WO03069658B1

公开(公告)日：2004-05-27

申请号：PCT/US0303352

申请日：2003-02-04

Applicant: IBM

Inventor： CHU JACK O ,  ISMAIL KHALED

IPC: H01L21/331 ,  H01L21/02 ,  H01L21/20 ,  H01L21/205 ,  H01L21/336 ,  H01L21/337 ,  H01L21/762 ,  H01L21/8238 ,  H01L27/08 ,  H01L27/092 ,  H01L27/12 ,  H01L29/161 ,  H01L29/165 ,  H01L29/73 ,  H01L29/78 ,  H01L29/786 ,  H01L27/00

CPC classification number: H01L29/78654 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02505 ,  H01L21/0251 ,  H01L21/02532 ,  H01L21/02664 ,  H01L21/76256 ,  H01L21/76259 ,  H01L29/66916 ,  H01L29/78603

Abstract: A method for fabricating a strained Si based layer, devices manufactured in this layer, and electronic systems comprising such layers and devices are disclosed. The method comprises the steps of growing epitaxially a SiGe layer on a substrate, and creating a varying Ge concentration in this SiGe layer. The Ge concentration in the SiGe layer includes a unique Ge overshoot zone, where the Ge concentration is abruptly and significantly increased. The Si based layer is epitaxially deposited onto the SiGe layer, whereby is becomes tensilely strained. It is also disclosed that the strained Si based layer, typically Si or SiGe, can be transferred to a different bulk substrate, or to an insulator.

Abstract translation: 公开了一种用于制造应变Si基层的方法，在该层中制造的器件以及包括这种层和器件的电子系统。 该方法包括在衬底上外延生长SiGe层并在该SiGe层中产生变化的Ge浓度的步骤。 SiGe层中的Ge浓度包括独特的Ge过冲区，其中Ge浓度突然显着增加。 Si基层外延沉积到SiGe层上，由此变得张紧应变。 还公开了可将应变Si基层（通常为Si或SiGe）转移到不同的块状衬底或绝缘体上。

公开(公告)号：MY127672A

公开(公告)日：2006-12-29

申请号：MYPI20000966

申请日：2000-03-11

Applicant: IBM

Inventor： CHU JACK O

IPC: H01L29/161 ,  H01L29/778 ,  H01L21/20 ,  H01L21/205 ,  H01L21/338 ,  H01L21/8232 ,  H01L21/8234 ,  H01L27/06 ,  H01L27/088 ,  H01L27/095 ,  H01L29/78 ,  H01L29/786 ,  H01L29/812

Abstract: A METHOD AND A LAYERED HETEROSTRUCTURE FOR FORMING HIGH MOBILITY GE CHANNEL FIELD EFFECT TRANSISTORS IS DESCRIBED INCORPORATING A PLURALITY OF SEMICONDUCTOR LAYERS ON A SEMICONDUCTOR SUBSTRATE, AND A CHANNEL STRUCTURE OF A COMPRESSIVELY STRAINED EPITAXIAL GE LAYER HAVING A HIGHER BARRIER OR A DEEPER CONFINING QUANTUM WELL AND HAVING EXTREMELY HIGH HOLE MOBILITY FOR COMPLEMENTARY MODFETS AND MOSFETS. THE INVENTION OVERCOMES THE PROBLEM OF A LIMITED HOLE MOBILITY DUE TO ALLOY SCATTERING FOR A P-CHANNEL DEVICE WITH ONLY A SINGLE COMPRESSIVELY STRAINED SIGE CHANNEL LAYER. THIS INVENTION FURTHER PROVIDES IMPROVEMENTS IN MOBILITY AND TRANSCONDUCTANCE OVER DEEP SUBMICRON STATE-OF-THE ART SI PMOSFETS IN ADDITION TO HAVING A BROAD TEMPERATURE OPERATION REGIME FROM ABOVE ROOM TEMPERATURE (425 K) DOWN TO CRYOGENIC LOW TEMPERATURES (0.4 K) WHERE AT LOW TEMPERATURES EVEN HIGH DEVICE PERFORMANCES ARE ACHIEVABLE.

公开(公告)号：MY127978A

公开(公告)日：2007-01-31

申请号：MYPI20022039

申请日：2002-06-03

Applicant: IBM

Inventor： CHRISTIANSEN SILKE H ,  CHU JACK O ,  GRILL ALFRED ,  MOONEY PATRICIA M

IPC: H01L21/84 ,  H01L21/20 ,  H01L21/265 ,  H01L21/762

Abstract: A METHOD TO OBTAIN THIN (

公开(公告)号：DE602005001401T2

公开(公告)日：2008-02-21

申请号：DE602005001401

申请日：2005-02-22

Applicant: IBM

Inventor： CHU JACK O ,  DEHLINGER GABRIEL K ,  GRILL ALFRED ,  KOESTER STEVEN J ,  OUYANG QIGING ,  SCHAUB JEREMY D

IPC: H01L31/101

Abstract: The invention addresses the problem of creating a high-speed, high-efficiency photodetector that is compatible with Si CMOS technology. The structure consists of a Ge absorbing layer on a thin SOI substrate, and utilizes isolation regions, alternating n- and p-type contacts, and low-resistance surface electrodes. The device achieves high bandwidth by utilizing a buried insulating layer to isolate carriers generated in the underlying substrate, high quantum efficiency over a broad spectrum by utilizing a Ge absorbing layer, low voltage operation by utilizing thin a absorbing layer and narrow electrode spacings, and compatibility with CMOS devices by virtue of its planar structure and use of a group IV absorbing material. The method for fabricating the photodetector uses direct growth of Ge on thin SOI or an epitaxial oxide, and subsequent thermal annealing to achieve a high-quality absorbing layer. This method limits the amount of Si available for interdiffusion, thereby allowing the Ge layer to be annealed without causing substantial dilution of the Ge layer by the underlying Si.