16.
    发明专利
    未知

    公开(公告)号:AT331252T

    公开(公告)日:2006-07-15

    申请号:AT02718297

    申请日:2002-03-18

    Applicant: IBM

    Abstract: A method and system for a distributed computing system having components like end nodes, switches, routers and links interconnecting packets over the interconnecting links. The switches and routers interconnect the end nodes and route the packets to the appropriate end node. The end nodes reassemble the packets into a message at a destination. A mechanism is provided to allow a single physical component to appear as multiple components each with unique control levels. These components may be host channel adapters (HCAs), target channel adapters (TCAs) or switches. A method and system for end node partitioning for a physical element is provided. A configuration of the physical element is selected. A port associated with the physical element is probed, wherein the port is probed with a subnet management packet by a subnet manager. In response to detecting a switch associated with the port, a local identifier is assigned to the port resulting in a configuration change of the physical element.

    método e equipamento para controle de acesso a adaptadores num ambiente computacional

    公开(公告)号:BR112012032854B1

    公开(公告)日:2021-05-11

    申请号:BR112012032854

    申请日:2010-11-08

    Applicant: IBM

    Abstract: método, equipamento, programa de computador e produto de programa de computador para controle de acesso a adaptadores num ambiente computacional o acesso a um adaptador de entrada/saída por configuração é controlado. para cada acesso solicitado ao adaptador, são feitas verificações para determinar se a configuração está autoriza-da a acessar o adaptador. se não estiver autorizada, então o acesso é negado. se estiver auto-rizada, mas o acesso estiver temporariamente bloqueado, a instrução de execução é alterada para indicar isso. se o acesso for permitido, mas o acesso deva ser bloqueado por outra razão (diferente do bloqueio temporário), 10 então o acesso é negado.

    TRANSLATION OF INPUT/OUTPUT ADDRESSES TO MEMORY ADDRESSES

    公开(公告)号:CA2800636C

    公开(公告)日:2018-03-13

    申请号:CA2800636

    申请日:2010-11-08

    Applicant: IBM

    Abstract: An address provided in a request issued by an adapter is converted to an address directly usable in accessing system memory. The address includes a plurality of bits, in which the plurality of bits includes a first portion of bits and a second portion of bits. The second portion of bits is used to index into one or more levels of address translation tables to perform the conversion, while the first portion of bits are ignored for the conversion. The first portion of bits are used to validate the address.

    STORE/STORE BLOCK INSTRUCTIONS FOR COMMUNICATING WITH ADAPTERS

    公开(公告)号:CA2800631C

    公开(公告)日:2018-02-13

    申请号:CA2800631

    申请日:2010-11-08

    Applicant: IBM

    Abstract: Communication with adapters of a computing environment is facilitated. Control instructions specifically designed for communicating data to and from the adapters are provided to facilitate the communication. The instructions explicitly target the adapters. Information provided in an instruction is used to steer the instruction to an appropriate location within the adapter, such as a Peripheral Component Interconnect (PCI) adapter or a Peripheral Component Interconnect Express (PCIe) adapter.

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