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    Soi cmos structure having programmable floating backplate
    11.
    发明专利
    Soi cmos structure having programmable floating backplate 未知

    公开(公告)号：GB2487492A

    公开(公告)日：2012-07-25

    申请号：GB201202931

    申请日：2010-11-02

    Applicant: IBM

    Inventor： NING TAK HUNG ,  CAI JIN ,  YAU JENG-BANG ,  KHAKIFIROOZ ALI ,  DENNARD ROBERT HEATH

    IPC: H01L21/84 ,  H01L27/12

    Abstract: SOI CMOS structures having at least one programmable electrically floating backplate are provided. Each electrically floating backplate is individually programmable. Programming can be performed by injecting electrons into each conductive floating backplate. Erasure of the programming can be accomplished by tunneling the electrons out of the floating backplate. At least one of two means can accomplish programming of the electrically floating backgate. The two means comprise Fowler-Nordheim tunneling, and hot electron injection using an SOI pFET. Hot electron injection using pFET can be done at much lower voltage than injection by tunneling electron injection.

    13.
    发明专利
    未知

    公开(公告)号：DE69406346D1

    公开(公告)日：1997-11-27

    申请号：DE69406346

    申请日：1994-04-06

    Applicant: IBM

    Inventor： DENNARD ROBERT HEATH

    IPC: H03K5/02 ,  G11C11/407 ,  G11C11/409 ,  H03K19/00 ,  H03K19/0185

    Abstract: The interface circuit of the present invention adjusts the signal voltage across a leaking transistor such that the leakage is reduced while also shunting out the adjustment means when the adjustment means impedes the operation of the interface circuit. One embodiment of the present invention is a level translator comprised of a level shifting stage coupled to a buffer stage. The level shifting stage has its power source coupled to a current shunting device. The current shunting device is connected in parallel across the first P-channel device of the level shifting stage. The first P-channel device of the level shifting stage is connected in series with a second P-channel device having its drain connected to a drain of a first N-channel device wherein the first N-channel device has its source connected to a drain of a second N-channel device. The current shunting device is formed from a single P-channel device. The connection between the drains of the second P-channel and the first N-channel device of the level shifting stage is an input to an inverter, which in turn, has its output connected to the input of the current shunting device. When the input to the level shift stage is at the high voltage logic signal level, the input to the inverter is low and the output of the inverter is at a high voltage logic signal level. The high voltage logic signal level then turns off the P-channel device of the current shunting device. The first P-channel device of the level shifting stage has its gate connected to its drain which reduces leakage current in the level shifting stage and reduces the power consumed by the interface circuit when the current shunting device is turned off. When the input to the level shift stage is at the low voltage logic signal level, the input to the inverter is high and the output of the inverter is at a low voltage logic signal level. The low voltage logic signal level allows the current shunting device to directly supply current to the second P-channel device of the level shifting stage and shunts out the first P-channel device. Therefore, the shunted out device does not interfere with the performance of the level shift stage of the interface circuit.

    CHARGE TRANSFER SENSING CIRCUITS
    14.
    发明专利
    CHARGE TRANSFER SENSING CIRCUITS 未知

    公开(公告)号：AU8328875A

    公开(公告)日：1977-01-27

    申请号：AU8328875

    申请日：1975-07-22

    Applicant: IBM

    Inventor： DENNARD ROBERT HEATH

    IPC: G11C11/409 ,  G11C7/06 ,  G11C11/24 ,  G11C11/401 ,  G11C11/404 ,  G11C11/4091 ,  G11C11/419 ,  H03F3/70 ,  G11C11/22 ,  G11C11/40

    Abstract: A differential charge transfer amplifier which functions as a sensing and regenerating circuit responsive to binary information represented by the level of charge in a stored charge memory cell is disclosed. The sense amplifier includes a pair of dummy cells and bucket brigade amplifiers which are connected on either side of a dynamic latching circuit which includes a plurality of actuable gate devices, which may be field effect transistors. A bit/sense line of the array is divided into two equal sections which are respectively connected to either side of the sense amplifier. The operation of the amplifier is cyclic, including a precharge period, a sensing period, a rewrite period and a restore period, after which the amplifier is in its original state. A feature of the amplifier is that it consumes no d.c. power other than leakage and has high sensitivity due to a charge transfer feature. Also, during the operation of the circuit, energy remaining in one of the bit line sections after rewriting is utilized to pre-bias both bit line sections to an initial level. As a result, this allows better control of the precharge level on the bit/sense line and in so doing, the power requirements are substantially reduced. At the same time, a dummy cell is charged to the potential of the now balanced bit lines.

    Complementary bipolar inverter
    16.
    发明专利
    Complementary bipolar inverter 未知

    公开(公告)号：GB2505612A

    公开(公告)日：2014-03-05

    申请号：GB201322170

    申请日：2012-04-15

    Applicant: IBM

    Inventor： CAI JIN ,  DENNARD ROBERT HEATH ,  HAENSCH WILFRIED E A ,  NING TAK HUNG

    IPC: H01L21/8228 ,  H01L21/84 ,  H01L27/082 ,  H01L27/12

    Abstract: An example embodiment is a complementary transistor inverter circuit. The circuit includes a semiconductor-on-insulator (SOI) substrate, a lateral PNP bipolar transistor fabricated on the SOI substrate, and a lateral NPN bipolar transistor fabricated on the SOI substrate. The lateral PNP bipolar transistor includes a PNP base, a PNP emitter, and a PNP collector. The lateral NPN bipolar transistor includes a NPN base, a NPN emitter, and a NPN collector. The PNP base, the PNP emitter, the PNP collector, the NPN base, the NPN emitter, and the NPN collector abut the buried insulator of the SOI substrate.

    18.
    发明专利
    未知

    公开(公告)号：DE2716691A1

    公开(公告)日：1977-12-01

    申请号：DE2716691

    申请日：1977-04-15

    Applicant: IBM

    Inventor： DENNARD ROBERT HEATH ,  RIDEOUT VINCENT LEO

    IPC: H01L27/10 ,  H01L21/28 ,  H01L21/316 ,  H01L21/336 ,  H01L21/762 ,  H01L21/8242 ,  H01L23/522 ,  H01L27/108 ,  H01L29/06 ,  H01L29/423 ,  H01L29/49 ,  H01L29/78 ,  H01L29/76 ,  H01L27/04

    Abstract: A field effect transistor (FET) with a unique gate structure is disclosed wherein the polycrystalline silicon (polysilicon) gate is self-aligned on its ends with respect to the conductive source and drain regions, and is self-aligned on its sides with respect to the nonconductive field isolation regions. The boundaries of these conductive and nonconductive regions determine the boundaries of the channel region of the FET. This double self-alignment feature results in a polysilicon gate, the lateral dimensions and location of which correlate directly with the lateral dimensions and location of the channel region of the FET. The unique gate fabrication technique employed according to the present invention comprises delineating lithographic patterns twice in the same polysilicon layer using the same oxidation barrier masking layer; whereby the first lithographic pattern delineates the FET device regions, and the next lithographic pattern forms the gate regions wherever the two patterns cross each other (i.e., wherever they delineate a common area).

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