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    METHOD AND STRUCTURE FOR FORMING HIGH-PERFORMANCE FETS WITH EMBEDDED STRESSORS
    2.
    发明申请
    METHOD AND STRUCTURE FOR FORMING HIGH-PERFORMANCE FETS WITH EMBEDDED STRESSORS 审中-公开
    用于形成具有嵌入式压力机的高性能FET的方法和结构

    公开(公告)号：WO2011037743A3

    公开(公告)日：2011-07-07

    申请号：PCT/US2010048039

    申请日：2010-09-08

    Applicant: IBM ,  CHENG KANGGUO ,  KHAKIFIROOZ ALI ,  DORIS BRUCE B ,  SHAHIDI GHAVAM

    Inventor： CHENG KANGGUO ,  KHAKIFIROOZ ALI ,  DORIS BRUCE B ,  SHAHIDI GHAVAM

    IPC: H01L29/78 ,  H01L21/336

    CPC classification number: H01L29/7848 ,  H01L21/2257 ,  H01L21/26586 ,  H01L29/165 ,  H01L29/41775 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7834

    Abstract: A high-performance semiconductor structure and a method of fabricating such a structure are provided. The semiconductor structure includes at least one gate stack (18), e.g., FET, located on an upper surface (14) of a semiconductor substrate (12). The structure further includes a first epitaxy semiconductor material (34) that induces a strain upon a channel (40) of the at least one gate stack. The first epitaxy semiconductor material is located at a footprint of the at least one gate stack substantially within a pair of recessed regions (28) in the substrate which are present on opposite sides of the at least one gate stack. A diffused extension region (38) is located within an upper surface of said first epitaxy semiconductor material in each of the recessed regions. The structure further includes a second epitaxy semiconductor material (36) located on an upper surface of the diffused extension region. The second epitaxy semiconductor material has a higher dopant concentration than the first epitaxy semiconductor material.

    Abstract translation: 提供了高性能半导体结构和制造这种结构的方法。 半导体结构包括位于半导体衬底（12）的上表面（14）上的至少一个栅叠层（18），例如FET。 该结构还包括在至少一个栅极堆叠的沟道（40）上引起应变的第一外延半导体材料（34）。 所述第一外延半导体材料位于所述至少一个栅极堆叠的基准面上，基本上位于所述衬底中的存在于所述至少一个栅极叠层的相对侧上的一对凹陷区域（28）内。 扩散延伸区域（38）位于每个凹陷区域中的所述第一外延半导体材料的上表面内。 该结构还包括位于扩散延伸区域的上表面上的第二外延半导体材料（36）。 第二外延半导体材料具有比第一外延半导体材料更高的掺杂剂浓度。

    Spannungslösung in PFET-Bereichen
    3.
    发明专利
    Spannungslösung in PFET-Bereichen 未知

    公开(公告)号：DE112016000183T5

    公开(公告)日：2017-08-24

    申请号：DE112016000183

    申请日：2016-01-04

    Applicant: IBM

    Inventor： RIM KERN ,  REZNICEK ALEXANDER ,  LU DARSEN DUANE ,  CHENG KANGGUO ,  DORIS BRUCE ,  KHAKIFIROOZ ALI

    IPC: H01L21/8238 ,  H01L21/336 ,  H01L29/78

    Abstract: Ein Verfahren zum Herstellen einer Halbleiter-Einheit beinhaltet ein Bereitstellen einer Struktur aus einem spannungsreichen Silicium auf einem Isolator (SSOI-Struktur), wobei die SSOI-Struktur eine auf einem Substrat (10) angeordnete dielektrische Schicht (20), eine auf der dielektrischen Schicht (20) angeordnete Silicium-Germanium-Schicht (30) sowie eine direkt auf der Silicium-Germanium-Schicht (30) angeordnete Schicht (40) aus einem spannungsreichen Halbleitermaterial aufweist, ein Bilden einer Mehrzahl von Rippen (43, 45) auf der SSOI-Struktur, ein Bilden einer Gate-Struktur (50) über einen Abschnitt von wenigstens einer Rippe in einem nFET-Bereich hinweg, ein Bilden einer Gate-Struktur (60) über einen Abschnitt von wenigstens einer Rippe in einem pFET-Bereich hinweg, ein Entfernen der Gate-Struktur (60) über den Abschnitt der wenigstens einen Rippe in dem pFET-Bereich hinweg, ein Entfernen der Silicium-Germanium-Schicht (30), die durch das Entfernen freigelegt wurde, sowie ein Bilden einer neuen Gate-Struktur (90) über den Abschnitt der wenigstens einen Rippe in dem pFET-Bereich hinweg, so dass die neue Gate-Struktur (90) den Abschnitt auf allen vier Seiten umgibt.

    METHODS OF FORMING FINFET SEMICONDUCTOR DEVICES USING A REPLACEMENT GATE TECHNIQUE AND THE RESULTING DEVICES
    4.
    发明专利
    METHODS OF FORMING FINFET SEMICONDUCTOR DEVICES USING A REPLACEMENT GATE TECHNIQUE AND THE RESULTING DEVICES 未知

    公开(公告)号：SG10201405677QA

    公开(公告)日：2015-05-28

    申请号：SG10201405677Q

    申请日：2014-09-12

    Applicant: GLOBALFOUNDRIES INC ,  IBM

    Inventor： XIE RUILONG ,  CAI XIUYU ,  CHENG KANGGUO ,  KHAKIFIROOZ ALI

    Abstract: A device includes first and second fins defined in a semiconductor substrate and a raised isolation post structure positioned between the first and second fins, wherein an upper surface of the raised isolation post structure is at a level that is approximately equal to or greater than a level corresponding to an upper surface of each of the first and second fins. A first space is defined by a sidewall of the first fin and a first sidewall of the raised isolation post structure, a second space is defined by a sidewall of the second fin and a second sidewall of the raised isolation post structure, and a gate structure is positioned around a portion of each of the first and second fins and around a portion of the raised isolation post structure, wherein at least portions of the gate structure are positioned in the first and second spaces.

    Local interconnect structure self-aligned to gate structure
    7.
    发明专利
    Local interconnect structure self-aligned to gate structure 未知

    公开(公告)号：GB2503176A

    公开(公告)日：2013-12-18

    申请号：GB201317939

    申请日：2012-01-16

    Applicant: IBM

    Inventor： KHAKIFIROOZ ALI ,  CHENG KANGGUO ,  DORIS BRUCE ,  HAENSCH WILFRIED E A ,  HARAN BALASUBRAMANIAN ,  KULKARNI PRANITA

    IPC: H01L21/8244 ,  H01L21/768 ,  H01L21/8234

    Abstract: A common cut mask is employed to define a gate pattern and a local interconnect pattern so that local interconnect structures and gate structures are formed with zero overlay variation relative to one another. A local interconnect structure may be laterally spaced from a gate structure in a first horizontal direction, and contact another gate structure in a second horizontal direction that is different from the first horizontal direction. Further, a gate structure may be formed to be collinear with a local interconnect structure that adjoins the gate structure. The local interconnect structures and the gate structures are formed by a common damascene processing step so that the top surfaces of the gate structures and the local interconnect structures are coplanar with each other.

    Soi cmos structure having programmable floating backplate
    8.
    发明专利
    Soi cmos structure having programmable floating backplate 未知

    公开(公告)号：GB2487492A

    公开(公告)日：2012-07-25

    申请号：GB201202931

    申请日：2010-11-02

    Applicant: IBM

    Inventor： NING TAK HUNG ,  CAI JIN ,  YAU JENG-BANG ,  KHAKIFIROOZ ALI ,  DENNARD ROBERT HEATH

    IPC: H01L21/84 ,  H01L27/12

    Abstract: SOI CMOS structures having at least one programmable electrically floating backplate are provided. Each electrically floating backplate is individually programmable. Programming can be performed by injecting electrons into each conductive floating backplate. Erasure of the programming can be accomplished by tunneling the electrons out of the floating backplate. At least one of two means can accomplish programming of the electrically floating backgate. The two means comprise Fowler-Nordheim tunneling, and hot electron injection using an SOI pFET. Hot electron injection using pFET can be done at much lower voltage than injection by tunneling electron injection.

    Method and structure for forming high-performance fets with embedded stressors
    9.
    发明专利
    Method and structure for forming high-performance fets with embedded stressors 未知

    公开(公告)号：GB2486839A

    公开(公告)日：2012-06-27

    申请号：GB201204634

    申请日：2010-09-08

    Applicant: IBM

    Inventor： CHENG KANGGUO ,  KHAKIFIROOZ ALI ,  DORIS BRUCE ,  SHAHIDI GHAVAM G

    IPC: H01L29/78 ,  H01L21/336

    Abstract: A high-performance semiconductor structure and a method of fabricating such a structure are provided. The semiconductor structure includes at least one gate stack (18), e.g., FET, located on an upper surface (14) of a semiconductor substrate (12). The structure further includes a first epitaxy semiconductor material (34) that induces a strain upon a channel (40) of the at least one gate stack. The first epitaxy semiconductor material is located at a footprint of the at least one gate stack substantially within a pair of recessed regions (28) in the substrate which are present on opposite sides of the at least one gate stack. A diffused extension region (38) is located within an upper surface of said first epitaxy semiconductor material in each of the recessed regions. The structure further includes a second epitaxy semiconductor material (36) located on an upper surface of the diffused extension region. The second epitaxy semiconductor material has a higher dopant concentration than the first epitaxy semiconductor material.

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