公开(公告)号：DE3168886D1

公开(公告)日：1985-03-28

申请号：DE3168886

申请日：1981-07-14

Applicant: IBM

Inventor： DOCKERTY ROBERT CHARLES ,  GARBARINO PAUL LOUIS

IPC: H01L27/10 ,  H01L21/28 ,  H01L21/321 ,  H01L21/60 ,  H01L21/768 ,  H01L21/8242 ,  H01L27/108 ,  H01L29/78 ,  H01L21/90 ,  G11C11/40 ,  H01L23/52 ,  H01L29/52

公开(公告)号：DE2744059A1

公开(公告)日：1978-04-13

申请号：DE2744059

申请日：1977-09-30

Applicant: IBM

Inventor： ABBAS SHAKIR AHMED ,  DOCKERTY ROBERT CHARLES

IPC: H01L29/78 ,  H01L21/265 ,  H01L21/331 ,  H01L21/74 ,  H01L21/762 ,  H01L21/8249 ,  H01L27/06 ,  H01L29/73 ,  H01L29/76 ,  H01L29/72

公开(公告)号：DE2657511A1

公开(公告)日：1977-07-07

申请号：DE2657511

申请日：1976-12-18

Applicant: IBM

Inventor： ABBAS SHAKIR AHMED ,  ANANTHA NARASIPUR GUNDAPPA ,  DOCKERTY ROBERT CHARLES

IPC: H01L21/8247 ,  G11C11/36 ,  G11C16/04 ,  H01L27/07 ,  H01L27/102 ,  H01L29/51 ,  H01L29/788 ,  H01L29/792 ,  H01L29/861 ,  H01L29/872 ,  H01L29/94 ,  G11C11/34

Abstract: 1503300 Semiconductor memory device INTERNATIONAL BUSINESS MACHINES CORP 16 Nov 1976 [31 Dec 1975] 47660/76 Heading H1K A semiconductor memory device comprises an electrode 18, Fig. 2, forming a Schottkybarrier contact with an epitaxial layer 13 of one conductivity type, the electrode overlying a region 14 of second conductivity type formed in a surface region of a substrate 11 of said one conductivity type, and an insulating layer 21, 22 around the Schottky-barrier contact overlain by a conductive layer 24 which is insulated from the said electrode, the arrangement being such that when a predetermined voltage is applied across the Schottky barrier, the electrons produced in the avalanche breakdown of the Schottky diode are trapped in the insulating layer. During the above mentioned write operation, the conductive layer 24, typically of doped polysilicon is held at a high positive potential as compared to the electrode 18 and the terminals 30, 33 are at zero potential. During a non-destructive read operation, a substantial current flows from the electrode 18 to the P + diffusion 14 because of the trapped charges forming a depletion region 45 in the epitaxial layer. The insulating layer typically comprises silicon oxide and silicon nitride sublayers and the polysilicon layer 24 is separated from the electrode 18 by a silicon dioxide layer 26. Electrical connection to the P+ region 14 is achieved through a P+ diffused zone and a metal electrode (not shown), whereas the electrical contact 33 is made either at the bottom of the substrate or at the top of the epitaxial layer through an N + diffused region. A member matrix comprising the memory devices formed at the cross-overs of metallized tracks (31a, 31b), and the P+ diffused zones (14a, 14b), Fig. 1 (not shown) is disclosed

公开(公告)号：DE69721148T2

公开(公告)日：2003-12-11

申请号：DE69721148

申请日：1997-07-09

Applicant: IBM

Inventor： DOCKERTY ROBERT CHARLES ,  FRAGA RONALD MAURICE ,  RAMIREZ CIRO NEAL ,  RAY SUDIPTA KUMAR ,  ROBBINS GORDON JAY

IPC: H05K7/20 ,  H01L23/12 ,  H01L23/32 ,  H01L23/40 ,  H01L23/498 ,  H05K3/34 ,  H05K3/36

Abstract: Structure and method for reinforcing a solder column grid array attachment of a ceramic or the like substrate to a printed circuit board, the reinforcement providing support for a heat sink which is bonded or affixed by pressure to a structural element of the substrate. In one form, the invention involves the concurrent formation of materially larger solder columns along the perimeter of the substrate in conjunction with the array of thin electrically interconnecting solder columns on the substrate. The reinforcing and electrical signal columns are thereafter aligned and attached by solder reflow to a corresponding pattern of pads on the printed circuit board. The heat sink is thermally connected to a structural element of the substrate by bonding or mechanical compression. Stresses in the solder columns caused by heat sink compressive forces or vibration induced flexing are materially decreased without adding complex or unique manufacturing operations.

公开(公告)号：SG60129A1

公开(公告)日：1999-02-22

申请号：SG1997003775

申请日：1997-10-17

Applicant: IBM

Inventor： DOCKERTY ROBERT CHARLES ,  FRAGA RONALD MAURICE ,  ROBBINS GORDON JAY ,  REYNOLDS CHARLES LEVERN JR ,  RAY SUDIPTA KUMAR ,  RAMIREZ CIRO NEAL

IPC: H01L21/60 ,  H01L23/498 ,  H05K1/11 ,  H05K3/34

Abstract: Supporting structure for a ball grid array surface mounted integrated circuit device composed of support solder formed at selective corner locations on the ball grid array surface of the integrated circuit device. In one form, L-shaped patterns of high melting temperature solder are formed along the axes defined by the ball grid array and are characterized in that cross sections of the L-shaped pattern match that of the solder balls along one axis, and represent a continuum of solder between solder ball locations along the other axis. Support solder can be added where necessary to provide both structural reinforcement and thermal conduction. Control of the cross section of the support solder ensures that surface tension effects of the molten low temperature reflow solder used to connect the integrated circuit device does not materially change the final relative spacing between the integrated circuit device balls and the underlying printed circuit board contacts.

公开(公告)号：DE2614698A1

公开(公告)日：1976-10-21

申请号：DE2614698

申请日：1976-04-06

Applicant: IBM

Inventor： ABBAS SHAKIR AHMED ,  DOCKERTY ROBERT CHARLES

IPC: G11C17/00 ,  G11C11/22 ,  G11C11/34 ,  G11C16/04 ,  H01L21/8247 ,  H01L29/788 ,  H01L29/792 ,  G11C17/04

Abstract: A non-volatile read mostly memory cell in a monocrystalline semiconductor body wherein the sensing of the information is achieved by measuring the substrate current. The cell includes spaced source and drain regions, a gate dielectric layer capable of trapping a charge, a substrate contact electrode; a means to induce a trapped charge into the gate dielectric layer, including a means to apply a voltage larger than the threshold voltage to the gate electrode to form an inversion layer, and a means to apply a voltage to the drain electrode causing channel current to flow; a means to remove the trapped charge, including a means to apply a voltage equal to or exceeding the avalanche voltage to the drain to cause avalanching; a means to determine the presence or absence of a charge in the gate dielectric including a means to apply a voltage to the gate which is larger than the threshold voltage and a voltage to the drain that is significantly less than the avalanche voltage, and a means to determine the substrate current.

公开(公告)号：DE2257648A1

公开(公告)日：1973-06-28

申请号：DE2257648

申请日：1972-11-24

Applicant: IBM DEUTSCHLAND

Inventor： BLEHER JOHANNES HARTMUT DR ,  CHANG CHI SHIH ,  DOCKERTY ROBERT CHARLES

IPC: H01L21/8247 ,  H01L21/00 ,  H01L27/10 ,  H01L29/74 ,  H01L29/788 ,  H01L29/792 ,  H01L19/00

Abstract: 1340830 Semi-conductor memory devices INTERNATIONAL BUSINESS MACHINES CORP 1 Dec 1972 [20 Dec 1971] 55489/72 Heading H1K A memory device consists of a silicon gated N-channel enhancement mode IGFET with a bi-stable switching diode consisting of a layer of niobium oxide sandwiched between layers of niobium and bismuth disposed on and wholly within the periphery of its drain region. A matrix of devices may be formed on a P-type silicon wafer by oxidizing its surface and etching the oxide to expose the device sites, depositing polycrystalline silicon overall and pattern etching it to delineate the gates and strips interconnecting them in rows and to expose the P type silicon at the source and drain sites, after which the source and drain regions are formed and the remaining polycrystalline silicon doped by donor diffusion. Electrodes are formed on these regions by alloying platinum to them, after which niobium is deposited on the drain electrode and its surface wet anodized and then coated with bismuth. The matrix is completed by provision of pairs of aluminium strips interconnecting the source and bismuth electrodes respectively in columns. Information is stored by applying word address signals to the silicon row conductors and appropriately poled bit writing signals between pairs of aluminium strips to switch the diode to its high or low resistance state. It is read out by gating the appropriate IGFET on and sensing whether or not a small voltage applied across the series circuit of the source-drain path and diode produces a current.