公开(公告)号：GB2495873A

公开(公告)日：2013-04-24

申请号：GB201300772

申请日：2011-06-08

Applicant: IBM

Inventor： CIDECIYAN ROY D ,  ELEFTHERIOU EVANGELOS ,  HAAS ROBERT ,  HU XIAOYU ,  ILIADIS ILIAS ,  PLETKA ROMAN A

IPC: G11C16/34 ,  G06F12/02

Abstract: The invention is directed to a method for wear-leveling cells or pages or sub- pages or blocks of a memory such as a flash memory, the method comprising: - receiving (S10) a chunk of data to be written on a cell or page or sub-page or block of the memory; - counting (S40) in the received chunk of data the number of times a given type of binary data '0' or Ί ' is to be written; and - distributing (S50) the writing of the received chunk of data amongst cells or pages or sub-pages or blocks of the memory such as to wear-level the memory with respect to the number of the given type of binary data '0' or Ί ' counted in the chunk of data to be written.

公开(公告)号：GB2485706A

公开(公告)日：2012-05-23

申请号：GB201202742

申请日：2010-09-07

Applicant: IBM

Inventor： ELEFTHERIOU EVANGELOS ,  HAAS ROBERT ,  HU XIAOYU

IPC: G06F3/06

Abstract: Methods and apparatus are provided for managing data in a data storage system (10) having a solid-state storage device (11) and alternative storage (12, 13). In an internal management process, such as garbage collection or wear-levelling, performed in the solid- state storage device (11), data is identified which needs to be moved in the device (11) for internal management of the solid-state storage (14). At least some of the data so identified is moved to the alternative storage (12, 13) instead of the solid-state storage (14). Metadata, indicating the location of data in the solid-state storage device (11) and the alternative storage, (12, 13) is maintained to track data movements.

公开(公告)号：DE602006009123D1

公开(公告)日：2009-10-22

申请号：DE602006009123

申请日：2006-07-03

Applicant: IBM

Inventor： ELEFTHERIOU EVANGELOS ,  OELCER SEDAT ,  JAQUETTE GLEN ALAN ,  JELITTO JENS ,  HUTCHINS ROBERT ALLAN

IPC: G11B20/10 ,  H04L25/03

Abstract: A read channel and method using that read channel are disclosed. The read channel comprises an analog to digital converter which asynchronously samples at a fixed rate an analog signal formed by reading a data track, where that data track was written to a data storage medium at a symbol rate and an interpolator interconnected with the analog to digital converter. The read channel further comprises a fractionally-spaced equalizer, where the interpolator provides an interpolated signal to the fractionally-spaced equalizer at an interpolation rate, where that interpolation rate is greater than the symbol rate. The fractionally-spaced equalizer forms a synchronous equalized signal. The read channel further comprises a gain control module interconnected with the fractionally-spaced equalizer, and a sequence detector interconnected with the gain control module.

公开(公告)号：AT442651T

公开(公告)日：2009-09-15

申请号：AT06792475

申请日：2006-07-03

Applicant: IBM

Inventor： ELEFTHERIOU EVANGELOS ,  OELCER SEDAT ,  JAQUETTE GLEN ,  JELITTO JENS ,  HUTCHINS ROBERT

IPC: G11B20/10 ,  H04L25/03

Abstract: A read channel and method using that read channel are disclosed. The read channel comprises an analog to digital converter which asynchronously samples at a fixed rate an analog signal formed by reading a data track, where that data track was written to a data storage medium at a symbol rate and an interpolator interconnected with the analog to digital converter. The read channel further comprises a fractionally-spaced equalizer, where the interpolator provides an interpolated signal to the fractionally-spaced equalizer at an interpolation rate, where that interpolation rate is greater than the symbol rate. The fractionally-spaced equalizer forms a synchronous equalized signal. The read channel further comprises a gain control module interconnected with the fractionally-spaced equalizer, and a sequence detector interconnected with the gain control module.

公开(公告)号：GB2355165B

公开(公告)日：2003-10-22

申请号：GB0016683

申请日：2000-07-07

Applicant: IBM

Inventor： CIDECIYAN ROY D ,  COKER JONATHAN D ,  ELEFTHERIOU EVANGELOS ,  GALBRAITH RICHARD L ,  TRUAX TODD

IPC: G11B20/14 ,  G11B20/18 ,  H03M5/14 ,  G06F11/10 ,  H03M7/14 ,  H03M7/42 ,  H03M13/01 ,  H03M13/05 ,  H03M13/31 ,  H04L1/00 ,  H04L25/49

Abstract: A method and apparatus for encoding a plurality of successive m-bit binary data words to produce a plurality of successive of n-bit binary code words, where n and m are positive integers and n is greater than m, for supply to a magnetic recording channel. Each m-bit binary data word is partitioned into a plurality of blocks of bits, and at least one said blocks of bits in each m-bit binary data word is encoded in accordance with a finite-state coding scheme to produce a plurality of successive n-bit binary code words. At least one stage of violation correction which transforms the plurality of successive n-bit binary code words. Violation correction includes detecting the occurrence of any of a plurality of prohibited bit patterns at one or more predetermined locations within each n-bit binary coded word, and replacing any prohibited bit pattern so detected by a corresponding substitute bit pattern. The finite-state coding scheme, the prohibited bit patterns, and corresponding substitute bit patterns are predetermined such that in a serial bit-steam comprising the successive n-bit binary code words, the maximum number of consecutive bits of a first value is limited to a first predetermined number j, where b greater or equal to 2, and the maximum number of consecutive bits of the a second value is limited to a second predetermined number k.

公开(公告)号：DE69314356T2

公开(公告)日：1998-03-26

申请号：DE69314356

申请日：1993-06-14

Applicant: IBM

Inventor： CHEVILLAT PIERRE ,  ELEFTHERIOU EVANGELOS ,  MAIWALD DIETRICH

IPC: G11B20/14 ,  G11B5/09 ,  G11B20/10 ,  H04L25/03 ,  H04L25/497

Abstract: PCT No. PCT/EP93/01500 Sec. 371 Date Jul. 20, 1995 Sec. 102(e) Date Jul. 20, 1995 PCT Filed Jun. 14, 1993 PCT Pub. No. WO94/29989 PCT Pub. Date Dec. 22, 1994The present application makes use of a novel adaptive noise-predictive partial-response equalization scheme for channels (30) exhibiting spectral nulls and/or near nulls. The noise-predictive partial-response (PR) equalizer employed in the different embodiments of the present invention consists of a linear PR equalizer (32) which shapes the channel response to a predetermined partial-response function, followed by a linear predictor. This scheme modifies the output sequence of said linear partial-response equalizer (32) by whitening the total distortion, i.e. by whitening the noise components and the residual interference components at said linear PR equalizer output, thereby achieving the best possible signal-to-noise ratio (SNR) before detection.

公开(公告)号：DE69314356D1

公开(公告)日：1997-11-06

申请号：DE69314356

申请日：1993-06-14

Applicant: IBM

Inventor： CHEVILLAT PIERRE ,  ELEFTHERIOU EVANGELOS ,  MAIWALD DIETRICH

IPC: G11B20/14 ,  G11B5/09 ,  G11B20/10 ,  H04L25/03 ,  H04L25/497

Abstract: PCT No. PCT/EP93/01500 Sec. 371 Date Jul. 20, 1995 Sec. 102(e) Date Jul. 20, 1995 PCT Filed Jun. 14, 1993 PCT Pub. No. WO94/29989 PCT Pub. Date Dec. 22, 1994The present application makes use of a novel adaptive noise-predictive partial-response equalization scheme for channels (30) exhibiting spectral nulls and/or near nulls. The noise-predictive partial-response (PR) equalizer employed in the different embodiments of the present invention consists of a linear PR equalizer (32) which shapes the channel response to a predetermined partial-response function, followed by a linear predictor. This scheme modifies the output sequence of said linear partial-response equalizer (32) by whitening the total distortion, i.e. by whitening the noise components and the residual interference components at said linear PR equalizer output, thereby achieving the best possible signal-to-noise ratio (SNR) before detection.

公开(公告)号：BR9408527A

公开(公告)日：1997-08-05

申请号：BR9408527

申请日：1994-02-10

Applicant: IBM

Inventor： ELEFTHERIOU EVANGELOS ,  PETERSEN BRENT ROBERT

IPC: H04B1/7103 ,  H04B3/06 ,  H04B7/26 ,  H04J13/00 ,  H04L25/03

Abstract: PCT No. PCT/EP94/00374 Sec. 371 Date Jun. 27, 1996 Sec. 102(e) Date Jun. 27, 1996 PCT Filed Feb. 10, 1994 PCT Pub. No. WO95/22209 PCT Pub. Date Aug. 17, 1995The present invention concerns an apparatus and method for reducing the multiuser-interference of input signals. The apparatus in accordance with the present invention comprises a multivariate predictor (81) and a decision quantizer (82), said multivariate predictor (81) operating on interference signals +E,uns eta +EE '(D) provided by means for extracting interference signals (83), said interference signals +E,uns eta +EE '(D) being obtained from said input signals and output signals +E,cir +E,uns b+EE +EE (D) which are available at an output of said decision quantizer (82) and fed back from there to said means for extracting interference signals (83).

公开(公告)号：DE112011100564B4

公开(公告)日：2021-08-26

申请号：DE112011100564

申请日：2011-01-07

Applicant: IBM

Inventor： PLETKA ROMAN ,  ELEFTHERIOU EVANGELOS ,  HAAS ROBERT ,  HU XIAO-YU ,  HSU YU-CHENG ,  GUPTA LOKESH MOHAN ,  HYDE II JOSEPH SMITH ,  BEN-HASE MICHAEL THOMAS ,  SANCHEZ ALFRED EMILIO ,  ASH KEVIN JOHN

IPC: G06F12/08

Abstract: Vorrichtung für das Einfügen eines Flash-basierten Caches in ein Speichersystem (200), wobei die Vorrichtung Folgendes umfasst:ein Eingabe-/Ausgabe(E/A)-Gehäuse (202a-n) mit einer Vielzahl von Steckplätzen für die Aufnahme von Hostadapters (208a-n) und Einheitenadapters (210a-n);einen Hostadapter, der in einem ersten Steckplatz des E/A-Gehäuses so eingesetzt ist, dass sich der Hostadapter in einem Innenraum des E/A-Gehäuses befindet, wobei der Hostadapter konfiguriert ist, um einen Host (204a-n) mit dem E/A-Gehäuse zu verbinden;einen Einheitenadapter (210a-n), der in einem zweiten Steckplatz des E/A-Gehäuses so eingesetzt ist, dass sich der Einheitenadapter in dem Innenraum des E/A-Gehäuses befindet, wobei der Einheitenadapter konfiguriert ist, um eine Speichereinheit (206a-n) mit dem E/A-Gehäuse zu verbinden;eine Flash-basierte Caching-Einheit („Flash-Cache“) (220an), die in einem dritten Steckplatz des E/A-Gehäuses so eingesetzt ist, dass sich der Flash-Cache in dem Innenraum des E/A-Gehäuses befindet, wobei der Flash-Cache einen Flash-basierten Speicher umfasst, der so konfiguriert ist, dass er Daten zwischenspeichert, die Datenanforderungen zugehörig sind, welche durch das E/A-Gehäuse verarbeitet werden, wobei der Flash-Cache in Bereiche unterteilt ist, die umfassen: einen Lese-Cachebereich (304), der Daten zwischenspeichert, die Lese-Datenanforderungen zugehörig sind, einen Schreib-Cachebereich (302), der Daten zwischenspeichert, die Schreib-Datenanforderungen zugehörig sind, einen Zusatz-Lese-Cachebereich (306), der einen Cache mit Daten verwaltet, die bereits in eine Speichereinheit ausgelagert wurden, so dass die Daten aus dem Zusatz-Lese-Cachebereich abgerufen werden können, und einen Speicherbereich (308) für das Speichern von Daten, die nicht in eine Speichereinheit ausgelagert wurden, so dass die Daten aus dem Speicherbereich abgerufen werden;einen primären Prozessorkomplex (214a) außerhalb des E/A-Gehäuses, der Datenanforderungen verwaltet, welche durch das E/A-Gehäuse verarbeitet werden, wobei der primäre Prozessorkomplex mit dem Hostadapter, dem Einheitenadapter und dem Flash-Cache Daten austauscht, um die Datenanforderungen zu verwalten, wobei der primäre Prozessorkomplex einen ersten DRAM-Cache (Dynamic Random Access Memory, dynamischer Arbeitsspeicher) (216a) für das vorübergehende Zwischenspeichern von Daten umfasst, die Datenanforderungen zugehörig sind, welche durch das E/A-Gehäuse verarbeitet werden, wobei der primäre Prozessorkomplex so konfiguriert ist, dass er Daten, die in dem ersten DRAM-Cache zwischengespeichert sind, in den Flash-Cache auslagert;einen sekundären Prozessorkomplex (214b) außerhalb des E/A-Gehäuses, der als eine sekundäre Verwaltungseinheit für Datenanforderungen dient, welche durch das E/A-Gehäuse verarbeitet werden, wobei der sekundäre Prozessorkomplex mit dem Hostadapter, dem Einheitenadapter und dem Flash-Cache Daten austauscht, um als Reaktion auf einen Ausfall des primären Prozessorkomplexes Datenanforderungen zu verwalten, wobei der sekundäre Prozessorkomplex einen zweiten DRAM-Cache (216b) für das vorübergehende Zwischenspeichern von Daten umfasst, die Datenanforderungen zugehörig sind, welche durch das E/A-Gehäuse verarbeitet werden, wobei der sekundäre Prozessorkomplex so konfiguriert ist, dass er Daten, die in dem zweiten DRAM-Cache zwischengespeichert sind, in den Flash-Cache auslagert.

公开(公告)号：CA2636848C

公开(公告)日：2015-04-28

申请号：CA2636848

申请日：2007-01-10

Applicant: IBM

Inventor： CHERUBINI GIOVANNI ,  ELEFTHERIOU EVANGELOS ,  JELITTO JENS ,  HUTCHINS ROBERT

IPC: G11B5/584

Abstract: A fully synchronous longitudinal position (LPOS) detection system is provided for improving the reliability of servo channels in tape systems. The system is based on the interpolation of the servo channel output signal, which is sampled by an analog-to-digital converter (ADC) at a fixed sampling rate, using a clock at a nominal frequency, so that interpolated signal samples are obtained at a predetermined fixed rate, independent of tape velocity. This predetermined fixed rate is defined in terms of samples per unit of length, as opposed to samples per unit of time, which is the measure of the ADC sampling rate. The resolution with which the servo channel signal is obtained at the interpolator output is thus determined by the step interpolation distance.