公开(公告)号：CA1140660A

公开(公告)日：1983-02-01

申请号：CA348133

申请日：1980-03-21

Applicant: IBM

Inventor： FANG FRANK F ,  HUNG ROLAND Y

IPC: H01L27/15 ,  H01L31/12 ,  H01L31/153 ,  H01S5/00 ,  H01S5/026 ,  H04B10/29 ,  H01L33/00 ,  H01L31/04

Abstract: ELECTROOPTICAL INTEGRATED CIRCUIT COMMUNICATION The overall performance of integrated circuit systems is enhanced by the use of optical drivers and receivers to send and receive information between the devices on the chip and between individual chips in a system. A single substrate of gallium arsenide employs both the high carrier mobility properties and the electrooptical signal conversion properties on a single substrate to provide both high performance electrical properties and high density and high performance communication properties. YO978-046

公开(公告)号：CA849678A

公开(公告)日：1970-08-18

申请号：CA849678D

Applicant: IBM

Inventor： HOWARD WEBSTER E JR ,  FANG FRANK F

公开(公告)号：CA1232370A

公开(公告)日：1988-02-02

申请号：CA502704

申请日：1986-02-25

Applicant: IBM

Inventor： FANG FRANK F ,  GROSSMAN BERTRAND M

IPC: H01L29/78 ,  H01L21/033 ,  H01L21/28 ,  H01L21/336 ,  H01L21/8236 ,  H01L29/41 ,  H01L29/423 ,  H01L21/38

Abstract: CONSTRUCTION OF SHORT-LENGTH ELECTRODE IN SEMICONDUCTOR DEVICE A construction process employs an insulating abutment which serves as a guide in the formation of a shortlength electrode in the fabrication of a semiconductor device. The process is particularly useful in construction of extremely short channel asymmetric lightly doped drain (LDD) silicon FET's in which case a bird beak is formed on the surface of a silicon wafer. The bird beak is composed of silicon dioxide produced by oxidation of the silicon substrate with the aid of an oxidation resistant covering of silicon nitride, the edge of which defines the location of the abutment. Reactive ion etching is employed to remove excess silicon dioxide leaving a vertical wall at one side of the abutment. Thereafter, the silicon nitride layer is stripped off leaving a slanting roof to the abutment. A doped polysilicon layer is deposited conformally on the surface of the substrate and on the abutment to a depth equal to the desired length of the electrode, in this case the desired length of the FET gate. Further reactive ion etching removes all of the polysilicon except for the portion thereof appended to the vertical wall of the abutment. Thereafter, ion implantation establishes a drain region at the side of the abutment having the slanting roof and a source region at the side of the abutment facing the vertical wall. The profile of the ion implantation follows the profile of the abutment enabling the stopping properties of the abutment to constrict the amount of charge implanted in the drain side of the channel thereby to establish a desired resistance and protection from avalanche breakdown.

公开(公告)号：CA1189981A

公开(公告)日：1985-07-02

申请号：CA430329

申请日：1983-06-14

Applicant: IBM

Inventor： FANG FRANK F ,  SAI-HALASZ GEORGE A

IPC: H01L29/76

Abstract: PUNCH THROUGH MODULATED SEMICONDUCTOR DEVICE A field effect transistor having operating characteristics based on the control and modulation of the punch through phenomenon. The channel region between the source and the drain regions is appropriately doped such that the source and drain depletion regions overlap when no potential is applied between source and drain. The overlapped region in the absence of a gate field has a potential barrier. A gate voltage modulates the barrier to below the kT/q parameter. The source-to-drain fields also modulate the barrier.

公开(公告)号：CA1073557A

公开(公告)日：1980-03-11

申请号：CA279129

申请日：1977-05-25

Applicant: IBM

Inventor： DOO VEN Y ,  FANG FRANK F

IPC: H05K3/46 ,  H01L21/98 ,  H01L23/02 ,  H01L23/04 ,  H01L23/538 ,  H01L25/065 ,  H02G3/16 ,  H05K7/20

Abstract: A MULTILAYER INTERCONNECT SYSTEM, AND METHOD OF MAKING A large scale integrated circuit multilayer interconnect system in which signal propagation delay is substantially reduced by using air as the dielectric between layers, rather than an insulating material. The system is comprised of a plurality of two basic layers, namely a signal plane layer and a reference plane layer. The basic layers are spaced from and alternated with one another by insulated spacers to maintain a desired air gap.

公开(公告)号：CA822843A

公开(公告)日：1969-09-09

申请号：CA822843D

Applicant: IBM

Inventor： FANG FRANK F ,  WALKER EDWARD J ,  YU HWA N

公开(公告)号：DE68909977T2

公开(公告)日：1994-05-05

申请号：DE68909977

申请日：1989-01-27

Applicant: IBM

Inventor： BRODSKY MARC H ,  FANG FRANK F ,  MEYERSON BERNARD S

IPC: H01L29/73 ,  H01L21/331 ,  H01L29/10 ,  H01L29/15 ,  H01L29/161 ,  H01L29/201 ,  H01L29/737 ,  H01L29/14

公开(公告)号：DE3072133D1

公开(公告)日：1988-12-22

申请号：DE3072133

申请日：1980-05-09

Applicant: IBM

Inventor： FANG FRANK F ,  HUNG ROLAND Y

IPC: H01L27/15 ,  H01L31/12 ,  H01L31/153 ,  H01S5/00 ,  H01S5/026 ,  H04B10/29 ,  H01L31/14 ,  H04B9/00

Abstract: A GaAs semiconductor integrated chip has circuit components (9, 10), an input photoelectric converter (4) providing input signals to said circuit components, and an output electrooptic converter (3) providing output signals from said circuit components. Optical fibres (6, 5) communicate the signals to and from the structure. An optical fibre (7) couples an electrooptic converter (18) and a photoelectric converter (13) to provide an on chip cross-over relative to an electrode (16).

公开(公告)号：CA1048113A

公开(公告)日：1979-02-06

申请号：CA236774

申请日：1975-09-30

Applicant: IBM

Inventor： FANG FRANK F

IPC: H03M1/12 ,  G11C11/44 ,  G11C27/02 ,  H01L39/22 ,  H03K7/02 ,  H03M1/00 ,  H03K3/38

Abstract: ANALOG WAVEFORM TRANSDUCING CIRCUIT An analog waveform transducing circuit is disclosed which includes a pair of superconductive circuits connected in parallel between a pair of terminals. One of these circuits includes a Josephson tunnelling device and the other includes inductance which is greater than the inductance of the Josephson device. An analog signal is applied to one of said terminals. Means are provided for switching said Josephson device between normal and superconductive states to thereby trap one or more flux quanta. An output means is coupled to one of the two circuits. In one embodiment the means for switching the Josephson device responds to the analog signal level only, that is the control current is fixed (or zero). In this embodiment a number of pulses may be produced which can be related to the signal level, so that the circuit is an analog to digital converter. In another embodiment the means for switching said Josephson device includes a control means which normally results in said Josephson device being in a resistive state so that substantially all of said analog signal flows in said second circuit. When the means for switching switches the Josephson device to the superconductive state the second circuit will pass a portion of the analog signal equal to the analog signal flowing therein prior to the switching of the Josephson device. That portion of the analog signal reflecting variations in the analog signal subsequent to switching will flow in the first circuit. This condition will persist for so long as the Josephson device remains in the superconductive state. Substantially all the analog signal will again flow in the second circuit after the Josephson device is again switched to the normal state by the means for switching. This embodiment performs a sample and hold function in that the analog signal level at the time of switching is maintained in the second circuit regardless of variations (within proper limits) of the analog signal level. The current flowing in the second circuit may then be measured by any utilization means to measure the analog signal level at the time of switching.

公开(公告)号：FR2376493A1

公开(公告)日：1978-07-28

申请号：FR7736215

申请日：1977-11-24

Applicant: IBM

Inventor： FANG FRANK F ,  YU HWA N

IPC: G11C11/401 ,  G11C16/04 ,  H01L21/8242 ,  H01L27/108 ,  H01L29/78 ,  H01L31/00 ,  G11C11/34 ,  G11C7/00