公开(公告)号：CA2130405A1

公开(公告)日：1995-05-18

申请号：CA2130405

申请日：1994-08-18

Applicant: IBM

Inventor： FUOCO DANIEL P ,  HERRING CHRISTOPHER M ,  KELLOGG MARK W ,  LENTO JORGE E

IPC: G06F11/10 ,  G06F11/20

Abstract: The present invention provides a computer system and method of using the same. Add-on memory cards for the system are provided which cards have error correction code logic on the card, and logic to do partial writes of data words. The system has a central processing unit (CPU), a BUS interconnecting the CPU and the add-on memory cards. The CPU or associated components are configured to write data and read data from the add-on memory as several data bytes constituting data words. The system is further configured either within the CPU or as a separate function to generate parity bits associated with each of the bytes of data the CPU writes to the add-on memory and to read parity bits associated with data the CPU reads from the add-on memory and regenerate new parity bits and compare the newly generated parity bits with the original parity bits to detect data errors on data read from the add-on memory. The system itself does not contain error correction code (ECC). The add-on memory has ECC logic to identify any byte having a single bit error in the data bytes or the parity bits written by the CPU to the add-on memory and to correct all single bit errors in data read from the add-on memory to the CPU. The error correcting code includes logic to generate parity bits in the data bytes written by the CPU to the add-on memory and logic to compare the parity bits written by the CPU with those generated by the error correcting code logic. Also provided is a circuitry card technique to block or by-pass error reporting and correcting during initialization.

公开(公告)号：BR9202063A

公开(公告)日：1993-02-02

申请号：BR9202063

申请日：1992-05-29

Applicant: IBM

Inventor： FUOCO DANIEL P ,  HERNANDEZ LUIS A ,  MATHISEN ERIC ,  RAYMOND JONATHAN H ,  TASHAKORI ESMAEIL

IPC: G01R31/02 ,  G01R31/04 ,  G01R31/319 ,  G06F11/273 ,  H05K1/00 ,  H01L27/00

公开(公告)号：CA2065997A1

公开(公告)日：1992-11-29

申请号：CA2065997

申请日：1992-04-14

Applicant: IBM

Inventor： FUOCO DANIEL P ,  HERNANDEZ LUIS A ,  MATHISEN ERIC ,  MOELLER DENNIS L ,  RAYMOND JONATHAN H ,  TASHAKORI ESMAEIL

IPC: G06F13/38 ,  G06F1/24 ,  G06F13/40 ,  G06F13/20

Abstract: This invention relates to personal computers, and more particularly to personal computers in which capability is provided for the usual system controlling processor to be reset, initialized and then isolated if an alternate system controller is provided for the system. In accordance with this invention, a personal computer system has a high speed local processor data bus; an input/output data bus; a microprocessor coupled directly to the local processor bus; a connector coupled directly to the local processor bus for accommodating reception of an alternate processor; and a bus interface controller coupled directly to the local processor bus and directly to the input/output data bus for providing communications between the local processor bus and the input/output data bus, with the bus interface controller providing for detection of the presence of an alternate processor received in the connector and, in response to detection of the presence of an alternate processor, transferring control of the local processor bus from the microprocessor to the alternate processor.

公开(公告)号：MX9202495A

公开(公告)日：1992-11-01

申请号：MX9202495

申请日：1992-05-27

Applicant: IBM

Inventor： FUOCO DANIEL P ,  HERNANDEZ LUIS ANTONIO ,  MATHISEN ERIC ,  MOELLER DENNIS LEE ,  RAYMOND JONATHAN HENRY ,  TASHAKORI ESMAEIL

IPC: G06F1/24 ,  G06F13/00 ,  G11C11/10

Abstract: This invention relates to personal computers, and more particularly to personal computers in which capability is provided for continuance of processing through an occurrence of a RESET signal while avoiding systems failures. The personal computer system has a high speed local processor data bus; an input/output data bus; a resettable microprocessor coupled directly to the local processor bus; and a bus interface controller coupled directly to the local processor bus and directly to the input/output data bus for providing communications between the local processor bus and input/output data bus. The bus interface controller provides for arbitration among devices directly coupled to the input/output data bus for access to the input/output data bus and to the local processor bus and for arbitration among the input/output data bus and the microprocessor for access to the local processor bus. The bus interface controller further recognizes receipt of a reset signal intended to initiate a reset of the microprocessor and defers delivery of a reset signal to until the bus interface controller has barred access to the local processor bus and input/output bus by any of the devices potentially requesting such access.