公开(公告)号：AU594169B2

公开(公告)日：1990-03-01

申请号：AU7524887

申请日：1987-07-06

Applicant: IBM

Inventor： GARNACHE RICHARD RAYMOND ,  KENNEY DONALD MACALPINE

IPC: H01L27/10 ,  H01L21/8242 ,  H01L27/108 ,  H01L27/04

Abstract: A memory is provided which includes a semiconductor substrate (26) having a major surface and a trench (24) disposed therein having a longitudinal axis, storage means (16, 16') disposed on a given sidewall of the trench, switching means (12, 12') having a control element and a current carrying element disposed on the given sidewall of the trench between the storage means and the major surface of the substrate and coupled to the storage means, a first electrically conductive line (40, 40') disposed on the given sidewall in contact with the control element of the switching means and having a longitudinal axis arranged parallel to the longitudinal axis of the trench, and a second electrically conductive line (22, 22') disposed on the major surface of the semiconductor substrate in contact with the current carrying electrode of the switching means and having a longitudinal axis arranged orthogonal to the longitudinal axis of the trench.

公开(公告)号：DE3379618D1

公开(公告)日：1989-05-18

申请号：DE3379618

申请日：1983-01-21

Applicant: IBM

Inventor： DASH SOMANATH ,  GARNACHE RICHARD RAYMOND ,  TROUTMAN RONALD ROY

IPC: H01L29/80 ,  H01L21/8238 ,  H01L27/08 ,  H01L27/092 ,  H01L27/12 ,  H01L29/49 ,  H01L29/78 ,  H01L29/786 ,  H01L21/82

公开(公告)号：NO872721A

公开(公告)日：1988-01-18

申请号：NO872721

申请日：1987-06-29

Applicant: IBM

Inventor： GARNACHE RICHARD RAYMOND ,  KENNEY DONALD MACALPINE

IPC: H01L27/10 ,  H01L21/8242 ,  H01L27/108 ,  G11C

CPC classification number: H01L27/10841

公开(公告)号：DE3072095D1

公开(公告)日：1988-06-30

申请号：DE3072095

申请日：1980-11-20

Applicant: IBM

Inventor： GARNACHE RICHARD RAYMOND ,  KENNEY DONALD MCALPINE

IPC: H01L21/28 ,  H01L21/306 ,  H01L21/336

Abstract: A method for providing self-aligned conductors in vertically integrated semiconductor devices which includes providing recesses in the surface of a semiconductor substrate for the fabrication of V-groove devices, providing a conductive layer over the surface and then applying a layer of masking material over the conductive layer to form a planar upper surface, selectively etching the masking material until it remains only in the recesses and then selectively etching the exposed portion of the conductive layer.

公开(公告)号：AU7524887A

公开(公告)日：1988-01-21

申请号：AU7524887

申请日：1987-07-06

Applicant: IBM

Inventor： GARNACHE RICHARD RAYMOND ,  KENNEY DONALD MACALPINE

IPC: H01L27/10 ,  H01L21/8242 ,  H01L27/108 ,  H01L27/04

Abstract: A memory is provided which includes a semiconductor substrate (26) having a major surface and a trench (24) disposed therein having a longitudinal axis, storage means (16, 16') disposed on a given sidewall of the trench, switching means (12, 12') having a control element and a current carrying element disposed on the given sidewall of the trench between the storage means and the major surface of the substrate and coupled to the storage means, a first electrically conductive line (40, 40') disposed on the given sidewall in contact with the control element of the switching means and having a longitudinal axis arranged parallel to the longitudinal axis of the trench, and a second electrically conductive line (22, 22') disposed on the major surface of the semiconductor substrate in contact with the current carrying electrode of the switching means and having a longitudinal axis arranged orthogonal to the longitudinal axis of the trench.

公开(公告)号：NO872721L

公开(公告)日：1988-01-18

申请号：NO872721

申请日：1987-06-29

Applicant: IBM

Inventor： GARNACHE RICHARD RAYMOND ,  KENNEY DONALD MACALPINE

IPC: H01L21/8242 ,  H01L27/10 ,  H01L27/108 ,  G11C

Abstract: A memory is provided which includes a semiconductor substrate (26) having a major surface and a trench (24) disposed therein having a longitudinal axis, storage means (16, 16') disposed on a given sidewall of the trench, switching means (12, 12') having a control element and a current carrying element disposed on the given sidewall of the trench between the storage means and the major surface of the substrate and coupled to the storage means, a first electrically conductive line (40, 40') disposed on the given sidewall in contact with the control element of the switching means and having a longitudinal axis arranged parallel to the longitudinal axis of the trench, and a second electrically conductive line (22, 22') disposed on the major surface of the semiconductor substrate in contact with the current carrying electrode of the switching means and having a longitudinal axis arranged orthogonal to the longitudinal axis of the trench.

公开(公告)号：NO872721D0

公开(公告)日：1987-06-29

申请号：NO872721

申请日：1987-06-29

Applicant: IBM

Inventor： GARNACHE RICHARD RAYMOND ,  KENNEY DONALD MACALPINE

IPC: H01L21/8242 ,  H01L27/10 ,  H01L27/108 ,  G11C

Abstract: A memory is provided which includes a semiconductor substrate (26) having a major surface and a trench (24) disposed therein having a longitudinal axis, storage means (16, 16') disposed on a given sidewall of the trench, switching means (12, 12') having a control element and a current carrying element disposed on the given sidewall of the trench between the storage means and the major surface of the substrate and coupled to the storage means, a first electrically conductive line (40, 40') disposed on the given sidewall in contact with the control element of the switching means and having a longitudinal axis arranged parallel to the longitudinal axis of the trench, and a second electrically conductive line (22, 22') disposed on the major surface of the semiconductor substrate in contact with the current carrying electrode of the switching means and having a longitudinal axis arranged orthogonal to the longitudinal axis of the trench.

公开(公告)号：DE3165658D1

公开(公告)日：1984-09-27

申请号：DE3165658

申请日：1981-05-25

Applicant: IBM

Inventor： GARNACHE RICHARD RAYMOND ,  KENNEY DONALD MCALPINE ,  THOMA NANDOR GYORGY

IPC: H01L21/28 ,  H01L21/768 ,  H01L21/8242 ,  H01L27/10 ,  H01L27/108 ,  H01L29/423 ,  H01L29/78 ,  H01L29/60 ,  H01L21/90

Abstract: High density VMOSFET devices, particularly single transistor memory cells, are provided by use of a series of simplified self-aligning process steps. Gate electrodes, source/drain regions and source/drain contacts are provided with the aid of an initial mask-less photoresist removal process in which a relatively thick layer of self-leveling photoresist is uniformly removed in order to define portions of a gate electrode within the recess of a V-groove. The gate electrode subsequently acts as a self-aligned mask to define implanted source/drain regions also within the V-groove and to enable second level interconnecting metallurgy contacts to be formed along the sidewalls of the V-groove.

公开(公告)号：AU6351973A

公开(公告)日：1975-06-12

申请号：AU6351973

申请日：1973-12-12

Applicant: IBM

Inventor： GARNACHE RICHARD RAYMOND ,  SMITH WILLIAM MICHAEL JR

IPC: H01L21/225 ,  H01L23/522 ,  H01L27/07 ,  H01L27/108 ,  G11C11/24 ,  G11C11/40 ,  H01L7/02 ,  H01L11/00 ,  H01L19/00 ,  H03K17/60

公开(公告)号：DE2327351A1

公开(公告)日：1974-01-03

申请号：DE2327351

申请日：1973-05-29

Applicant: IBM

Inventor： GARNACHE RICHARD RAYMOND ,  GHATALIA ASHWIN KANTILAL ,  MICHAUD RONALD ADRIAN

IPC: C23F4/00 ,  B01J15/00 ,  C23C16/44 ,  C23C16/54 ,  C30B25/02 ,  C30B25/14 ,  C30B31/10 ,  C30B31/16 ,  H01L21/205 ,  H01L21/22 ,  H01L21/302 ,  H01L21/31 ,  C23C11/00