中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

21 records (took 0.015 seconds)

    METHOD FOR FORMING INTEGRATED CIRCUITS HAVING A PATTERN OF NARROW DIMENSIONED DIELECTRIC REGIONS
    12.
    发明专利
    METHOD FOR FORMING INTEGRATED CIRCUITS HAVING A PATTERN OF NARROW DIMENSIONED DIELECTRIC REGIONS 未知

    公开(公告)号：DE3177099D1

    公开(公告)日：1989-10-05

    申请号：DE3177099

    申请日：1981-06-23

    Applicant: IBM

    Inventor： GOTH GEORGE RICHARD ,  MAGDO INGRID EMESE ,  MALAVIYA SHASHI DHAR

    IPC: H01L21/3205 ,  H01L21/033 ,  H01L21/28 ,  H01L21/302 ,  H01L21/3065 ,  H01L21/3213 ,  H01L21/331 ,  H01L21/336 ,  H01L21/60 ,  H01L29/41 ,  H01L29/417 ,  H01L29/73 ,  H01L29/732 ,  H01L29/78 ,  H01L21/00 ,  H01L21/31

    Abstract: A method for forming integrated circuits having a pattern of narrow dimensioned dielectric regions and, more particularly self-aligned metal process is described which achieves self-aligned metal to silicon contacts and sub-micron contact-to-contact and metal-to-metal spacing. The insulation between the contacts and the metal is a pattern of dielectric material having a thickness dimension in the order of a micron or less. The metal or dielectric structure is substantially planar. The method of forming integrated circuits with this structure involves providing a silicon body (50, 51) and then forming a first insulating layer (52) on a major surface of the silicon body. A layer of polycrystalline silicon (53) is formed thereover. Openings are made in the polycrystalline silicon layer by reactive ion etching which results in the structure having substantially horizontal surfaces and substantially vertical surfaces. A second insulating layer (55) is then formed on both the substantially horizontal surfaces and substantially vertical surfaces. Reactive ion etching of this second insulating layer substantially removes the horizontal layers and provides a narrow dimensioned dielectric pattern of regions (56) on the major surface of the silicon body (50). The remaining polycrystalline silicon layer (53) is then removed by etching to leave the narrow dimensioned regions (56) on the major surfaces of the silicon body. A conductive layer is blanket desposited over the narrow dimensioned regions and areas in between. A blanket layer of a plastic material over the conductive layer to planarize the surface is accomplished. Reactive ion etching the plastic material and the conductive layer is continued until the tops of the narrow dimensioned regions (56) are reached leaving the structure of patterns (59 to 64) of metal filling the regions between the pattern of dielectric material having a thickness dimension in the order of a micron or less.

    15.
    发明专利
    未知

    公开(公告)号：DE3586554T2

    公开(公告)日：1993-04-08

    申请号：DE3586554

    申请日：1985-06-03

    Applicant: IBM

    Inventor： GOTH GEORGE RICHARD ,  HANSEN THOMAS ADRIAN ,  MAKRIS JAMES STEVE

    IPC: H01L21/761 ,  H01L21/302 ,  H01L21/3065 ,  H01L21/74 ,  H01L21/76 ,  H01L21/762 ,  H01L29/41

    Abstract: Deep trenches (14, 15) are formed according to the desired pattern through the N epitaxial layer (13) and N + subcollector region (12) into the P- substrate (11) of a silicon structure (10). Where a substrate contact is needed, the trenches delineate a central stud (16) or mesa of silicon material. Channel stop regions (18) are formed e.g. by ion implantation of boron atoms at the bottom of trenches. Si0 2 and Si 3 N 4 layers (17, 19) are then deposited on the whole structure. A substrate contact mask is applied and patterned to selectively expose one side of the trench sidewalls, the bottom of the trenches adjacent thereto and others areas if desired such as the top surface of the stud. The composite SiO 2 /Si 3 N 4 layer is then etched to leave exposed only the sidewalls of the stud, at least partially the bottom of the trenches adjacent thereto and the top surface of the stud. Platinum is deposited preferably via sputter deposition, conformally coating all regions of the structure. After sintering, the unreacted platinum is removed using wet chemical etch (aqua regia). Platinum silicide is left in all opened contacts and on the stud sidewalls where its defines a metal silicide lining (25) or cap, covering the stud. This lining connects the top surface (25a) of the stud, with the channel stop implanted regions (18) and thence forms the desired substrate contact.

    16.
    发明专利
    未知

    公开(公告)号：DE3687628D1

    公开(公告)日：1993-03-11

    申请号：DE3687628

    申请日：1986-10-28

    Applicant: IBM

    Inventor： GOTH GEORGE RICHARD

    IPC: H01L21/76 ,  H01L21/762 ,  H01L29/06

    Abstract: In a semiconductor structure having two highly and similarly doped, e.g., P+ type, regions (26,30) embedded in close juxtaposition in a trench-isolated N type silicon mesa (22), N+ channel stops (40,42) embedded in the N type mesa between the P type regions, are provided. The channel stops are self-aligned to the walls of trench to arrest charge leakage between the P type regions due to parasitic transistor action along the trench wall. The P type regions may constitute two resistors, the emitter and collector of a lateral PNP transistor, etc. The dopant concentration in the channel stops is about one to two orders of magnitude higher than that in the N type silicon. A process of forming such channel stops introduces N type dopant into the exposed silicon followed by an anneal step to laterally diffuse the dopant into the silicon body. The exposed silicon is etched forming a deep trench which delineates silicon mesa having at a section of the peripheral portion thereof a shallow and highly N doped region.

    18.
    发明专利
    未知

    公开(公告)号：DE3586554D1

    公开(公告)日：1992-10-01

    申请号：DE3586554

    申请日：1985-06-03

    Applicant: IBM

    Inventor： GOTH GEORGE RICHARD ,  HANSEN THOMAS ADRIAN ,  MAKRIS JAMES STEVE

    IPC: H01L21/761 ,  H01L21/302 ,  H01L21/3065 ,  H01L21/74 ,  H01L21/76 ,  H01L21/762 ,  H01L29/41

    Abstract: Deep trenches (14, 15) are formed according to the desired pattern through the N epitaxial layer (13) and N + subcollector region (12) into the P- substrate (11) of a silicon structure (10). Where a substrate contact is needed, the trenches delineate a central stud (16) or mesa of silicon material. Channel stop regions (18) are formed e.g. by ion implantation of boron atoms at the bottom of trenches. Si0 2 and Si 3 N 4 layers (17, 19) are then deposited on the whole structure. A substrate contact mask is applied and patterned to selectively expose one side of the trench sidewalls, the bottom of the trenches adjacent thereto and others areas if desired such as the top surface of the stud. The composite SiO 2 /Si 3 N 4 layer is then etched to leave exposed only the sidewalls of the stud, at least partially the bottom of the trenches adjacent thereto and the top surface of the stud. Platinum is deposited preferably via sputter deposition, conformally coating all regions of the structure. After sintering, the unreacted platinum is removed using wet chemical etch (aqua regia). Platinum silicide is left in all opened contacts and on the stud sidewalls where its defines a metal silicide lining (25) or cap, covering the stud. This lining connects the top surface (25a) of the stud, with the channel stop implanted regions (18) and thence forms the desired substrate contact.

Patent Agency Ranking