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11.发明专利
公开(公告)号：CA788930A
公开(公告)日：1968-07-02
申请号：CA788930D
Applicant: IBM
Inventor： CASWELL HOLLIS L , GREGOR LAWRENCE V , MCGEE HANSEL L
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公开(公告)号：FR2356447A1
公开(公告)日：1978-01-27
申请号：FR7714016
申请日：1977-05-03
Applicant: IBM
Inventor： DOUGHERTY WILLIAM E JR , GREGOR LAWRENCE V , KLEIN DONALD L , REDMOND THOMAS F , REEBER MORTON D
Abstract: A device for removing contaminant impurities, particularly contaminants existing at very low levels, from a liquid, including a heating element at least partially immersible in the liquid, a confinement means at least partially immersible in the liquid for maintaining a pulsating bubble of vapor of the liquid, the heating element located within the confining means, openings in the confining means to allow periodic partial escape of the vapor bubble and ingress of liquid.
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公开(公告)号：CA807138A
公开(公告)日：1969-02-25
申请号：CA807138D
Applicant: IBM
Inventor： GREGOR LAWRENCE V , CONNELL RICHARD A
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公开(公告)号：DE3072031D1
公开(公告)日：1987-10-22
申请号：DE3072031
申请日：1980-06-03
Applicant: IBM
Inventor： CARPENTER CHARLES , FUGARDI JOSEPH F , GREGOR LAWRENCE V , GROSEWALD PETER SAMUEL , REEBER MORTON D
IPC: B23K35/00 , H01L21/60 , H01L23/532 , H01L23/48
Abstract: A ball limiting metallurgy pad structure for a semiconductor device solder bond interconnection comprising: a conductive layer that is adherent to the semiconductor device passivating layer, a relatively thick layer of a material having a high thermal conductivity, a barrier layer that protects the high conductivity layer by physically preventing any interaction or alloying with the subsequent layers, and a layer of a material that is solder wettable.
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公开(公告)号：IT8022509D0
公开(公告)日：1980-06-03
申请号：IT2250980
申请日：1980-06-03
Applicant: IBM
Inventor： CHARLES CARPENTER , FUGARDI JOSEPH F , GREGOR LAWRENCE V , PETER GROSEWALD SAMUEL , REEBER MORTON D
IPC: B23K35/00 , H01L21/60 , H01L23/532 , H01L
Abstract: A ball limiting metallurgy pad structure for a semiconductor device solder bond interconnection comprising: a conductive layer that is adherent to the semiconductor device passivating layer, a relatively thick layer of a material having a high thermal conductivity, a barrier layer that protects the high conductivity layer by physically preventing any interaction or alloying with the subsequent layers, and a layer of a material that is solder wettable.
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Patent Agency Ranking
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公开(公告)号：IT1148836B
公开(公告)日：1986-12-03
申请号：IT2250980
申请日：1980-06-03
Applicant: IBM
Inventor： CARPENTER CHARLES , FUGARDI JOSEPH F , GREGOR LAWRENCE V , GROSEWALD SAMUEL PETER , REBBER MORTON D
IPC: B23K35/00 , H01L21/60 , H01L23/532 , H01L
Abstract: A ball limiting metallurgy pad structure for a semiconductor device solder bond interconnection comprising: a conductive layer that is adherent to the semiconductor device passivating layer, a relatively thick layer of a material having a high thermal conductivity, a barrier layer that protects the high conductivity layer by physically preventing any interaction or alloying with the subsequent layers, and a layer of a material that is solder wettable.
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公开(公告)号：CA1139008A
公开(公告)日：1983-01-04
申请号：CA349744
申请日：1980-04-14
Applicant: IBM
Inventor： CARPENTER CHARLES , FUGARDI JOSEPH F , GREGOR LAWRENCE V , GROSEWALD PETER S , REEBER MORTON D
IPC: B23K35/00 , H01L21/60 , H01L23/532 , H05K1/11
Abstract: METHOD OF FORMING AN IMPROVED SOLDER INTERCONNECTION BETWEEN A SEMICONDUCTOR DEVICE AND A SUPPORTING SUBSTRATE A ball limiting metallurgy pad structure for a semiconductor device solder bond interconnection comprises a conductive layer that is adherent to the semiconductor device passivating layer, a relatively thick layer of a material that has a high thermal conductivity, a barrier layer that protects the high conductivity layer by physically preventing it from interacting or alloying with any subsequent layers, and a layer of a material that is solder wettable.
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公开(公告)号：FR2282720A1
公开(公告)日：1976-03-19
申请号：FR7521476
申请日：1975-07-03
Applicant: IBM
Inventor： GREGOR LAWRENCE V , SHEPHEARD ROBERT G
IPC: H01L25/18 , H01L21/60 , H01L23/06 , H01L23/14 , H01L23/15 , H01L23/52 , H01L23/538 , H01L25/04 , H01L23/50
Abstract: 1477544 Semiconductor assemblies INTERNATIONAL BUSINESS MACHINES CORP 20 May 1975 [19 Aug 1974] 21597/75 Headings H1K and H1R A semiconductor assembly comprises a monocrystalline silicon member 16, in particular a silicon integrated circuit device, provided with a plurality of electrical contacts, a silicon nitride (Si 3 N 4 ) support substrate 10, Fig. 2, having co-efficient of thermal expansion closely corresponding to that of the silicon member and electrical contacts registering with the contacts of the silicon member, the contacts of the substrate and the silicon member being electrically joined by metallurgical bonds 17, e.g. solder bonds or ultrasonic solid bonds, so that the substrate and the silicon member are spared from each other; and an electrically conductive pattern 14 on the substrate 10 providing external connections. In the embodiment of Fig. 3, silicon integrated circuit devices 16 are bonded to a moncrystalline silicon member 20 in the manner described above, there being interconnection pattern formed on the member 20 by utilizing known masking and diffusion techniques or by depositing a conductive pattern or an insulating layer on the silicon member, and the silicon member 20 is in turn mounted on the silicon nitride support substrate through solder bonds or ultrasonic solid bonds 26. Pins 12 may be provided on the substrate for providing electrical connectons with a card or board 24. The substrate 10 is formed by compacting silicon nitride particles into the desired shape and sintering, on it may be formed by deposition.
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20.发明专利
公开(公告)号：CA915829A
公开(公告)日：1972-11-28
申请号：CA915829D
Applicant: IBM
Inventor： GREGOR LAWRENCE V , MAISSEL LEON I
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