公开(公告)号：WO2009109445A3

公开(公告)日：2009-12-10

申请号：PCT/EP2009051541

申请日：2009-02-11

Applicant: IBM ,  IBM UK ,  GUHA SUPRATIK ,  GUNAWAN OKI

Inventor： GUHA SUPRATIK ,  GUNAWAN OKI

IPC: H01L31/0232 ,  H01L31/0352 ,  H01L31/072

CPC classification number: H01L31/035281 ,  B82Y20/00 ,  H01L31/0216 ,  H01L31/072 ,  H01L31/1884 ,  Y02E10/50

Abstract: Photovoltaic devices and techniques for enhancing efficiency thereof are provided. In one aspect, a photovoltaic device is provided. The photovoltaic device comprises a photocell having a first photoactive layer and a second photoactive layer adjacent to the first photoactive layer so as to form a heterojunction between the first photoactive layer and the second photoactive layer; and a plurality of high-aspect-ratio nanostructures on one or more surfaces of the second photoactive layer. The plurality of high-aspect-ratio nanostructures are configured to act as a scattering media for incident light. The plurality of high-aspect-ratio nanostructures can also be configured to create an optical resonance effect in the incident light.

Abstract translation: 提供了用于提高效率的光伏器件和技术。 一方面，提供一种光电器件。 光电器件包括具有第一光活性层的光电池和与第一光活性层相邻的第二光活性层，以在第一光活性层和第二光活性层之间形成异质结; 以及在所述第二光敏层的一个或多个表面上的多个高纵横比纳米结构。 多个高纵横比纳米结构被配置为用作入射光的散射介质。 多个高纵横比纳米结构也可以被配置为在入射光中产生光学共振效应。

公开(公告)号：JP2002246594A

公开(公告)日：2002-08-30

申请号：JP2001388832

申请日：2001-12-21

Applicant: IBM

Inventor： BOJARCZUK NESTOR A JR ,  CARTIER EDUARD ,  GUHA SUPRATIK ,  RAGNARSSON LARS-AKE

IPC: H01L29/78 ,  H01L21/28 ,  H01L21/316 ,  H01L21/318 ,  H01L29/51

Abstract: PROBLEM TO BE SOLVED: To provide a method and structure for using a thin gate dielectric substance in a semiconductor device, such as a field effect transistor, etc. SOLUTION: The structure (for example, a field effect transistor) and a method for manufacturing the structure are provided with a substrate having a source region, a drain region, and a channel region provided between the source and drain regions, an insulating layer arranged on the channel region, and a gate electrode arranged on the insulating layer. The insulating layer includes an aluminum nitride-containing layer arranged on the channel region.

公开(公告)号：JPH10214992A

公开(公告)日：1998-08-11

申请号：JP883298

申请日：1998-01-20

Applicant: IBM

Inventor： BOJARCZUK NESTOR A JR ,  GUHA SUPRATIK ,  HAIGHT RICHARD ALAN

IPC: H01L33/08 ,  H01L33/50 ,  H01L51/00 ,  H01L51/30 ,  H01L51/50 ,  H01L33/00

Abstract: PROBLEM TO BE SOLVED: To emit an ultraviolet or blue light which can be converted efficiently into a visible light by applying a photoluminescence, in the form of an organic layer, onto an electroluminescence principally comprising inorganic GaN. SOLUTION: Al is deposited on a sapphire substrate 21 and subjected to a flow of excited nitrogen atoms and molecules in order to grow an AlN nucleus formation layer before Ga and Si are deposited thermally and an Si doped n-type GaN layer 12 is grown. Subsequently, Mg is deposited thermally and an Mg doped p-type GaN layer 14 is grown. Thereafter, an electric contact 16 to the p-type GaN layer 14 is formed by electron beam vacuum deposition of Ni/Au/Al and a part of the device structure is removed by etching thus exposing an n-type doped region 12 for second electric contact 18. Finally, the device is placed in a vacuum chamber and applied with a thin layer 20 of color conversion organic substance, i.e., Alq3 , by thermal deposition.

公开(公告)号：WO2005122286A3

公开(公告)日：2009-04-16

申请号：PCT/US2005010825

申请日：2005-03-30

Applicant: IBM ,  BOJARCZUK NESTOR A JR ,  CABRAL CYRIL JR ,  CARTIER EDUARD A ,  COPEL MATTHEW W ,  FRANK MARTIN M ,  GOUSEV EVGENI P ,  GUHA SUPRATIK ,  JAMMY RAJARAO ,  NARAYANAN VIJAY ,  PARUCHURI VAMSI K

Inventor： BOJARCZUK NESTOR A JR ,  CABRAL CYRIL JR ,  CARTIER EDUARD A ,  COPEL MATTHEW W ,  FRANK MARTIN M ,  GOUSEV EVGENI P ,  GUHA SUPRATIK ,  JAMMY RAJARAO ,  NARAYANAN VIJAY ,  PARUCHURI VAMSI K

IPC: H01L29/792 ,  H01L21/28 ,  H01L21/8238 ,  H01L29/49 ,  H01L29/51 ,  H01L31/113 ,  H01L31/119

CPC classification number: H01L29/513 ,  H01L21/28079 ,  H01L21/28088 ,  H01L21/823857 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/517

Abstract: A method of forming a CMOS structure, and the device produced therefrom, having improved threshold voltage and flatband voltage stability. The inventive method includes the steps of providing a semiconductor substrate having an nFET region and a pFET region; forming a dielectric stack atop the semiconductor substrate comprisisng an insulating interlayer atop a high k dielectric; removing the insulating interlayer from the nFET region without removing the insulating interlayer from the pFET region; and providing at least one gate stack in the pFET region and at least one gate stack in the nFET region. The insulating interlayer can be A1N or A1OxNY. The high k dielectric can be HfO2, hafnium silicate or hafnium silicon oxynitride. The insulating interlayer can be removed from the nFET region by a wet etch including a HC1/H2O2 peroxide solution.

Abstract translation: 一种形成CMOS结构的方法及其制造的器件，具有改进的阈值电压和平带电压稳定性。 本发明的方法包括提供具有nFET区和pFET区的半导体衬底的步骤; 在半导体衬底顶部形成介电堆叠，其中包括在高k电介质顶部的绝缘夹层; 从nFET区域去除绝缘中间层而不从pFET区域去除绝缘中间层; 以及在pFET区域中提供至少一个栅极堆叠以及在nFET区域中提供至少一个栅极叠层。 绝缘中间层可以是AlN或AlOxNY。 高k电介质可以是HfO 2，硅酸铪或铪硅氮氧化物。 可以通过包括HC1 / H2O2过氧化物溶液的湿蚀刻从nFET区域去除绝缘中间层。

公开(公告)号：WO2007087127A3

公开(公告)日：2007-11-22

申请号：PCT/US2007000161

申请日：2007-01-03

Applicant: IBM ,  CHUDZIK MICHAEL P ,  DORIS BRUCE B ,  GUHA SUPRATIK ,  JAMMY RAJARAO ,  NARAYANAN VIJAY ,  PARUCHURI VAMSI K ,  WANG YUN Y ,  KWONG HON WONG KEITH

Inventor： CHUDZIK MICHAEL P ,  DORIS BRUCE B ,  GUHA SUPRATIK ,  JAMMY RAJARAO ,  NARAYANAN VIJAY ,  PARUCHURI VAMSI K ,  WANG YUN Y ,  KWONG HON WONG KEITH

IPC: H01L21/336

CPC classification number: H01L29/517 ,  H01L21/28088 ,  H01L21/823828 ,  H01L21/823857 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/78 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Semiconductor structures, such as, for example, field effect transistors (FETs) and/or metal- oxide-semiconductor capacitor (MOSCAPs), are provided in which the workfunction of a conductive electrode stack is changed by introducing metal impurities into a metal-containing material layer which, together with a conductive electrode, is present in the electrode stack. The choice of metal impurities depends on whether the electrode is to have an n-type workfunction or a p-type workfunction. The present invention also provides a method of fabricating such semiconductor structures. The introduction of metal impurities can be achieved by codeposition of a layer containing both a metal-containing material and workfunction altering metal impurities, forming a stack in which a layer of metal impurities is present between layers of a metal-containing material, or by forming a material layer including the metal impurities above and/or below a metal-containing material and then heating the structure so that the metal impurities are introduced into the metal-containing material.

Abstract translation: 提供半导体结构，例如场效应晶体管（FET）和/或金属氧化物半导体电容器（MOSCAP），其中通过将金属杂质引入到含金属的物质中来改变导电电极堆叠的功函数 材料层与导电电极一起存在于电极堆叠中。 金属杂质的选择取决于电极是否具有n型功函数或p型功函数。 本发明还提供一种制造这种半导体结构的方法。 金属杂质的引入可以通过共沉积含有金属的材料和改变金属杂质的功函数的层来形成，形成其中金属杂质层存在于含金属材料的层之间的叠层，或通过形成 包括在含金属材料上方和/或下面的金属杂质的材料层，然后加热该结构，使得金属杂质被引入到含金属的材料中。

公开(公告)号：WO2011061043A3

公开(公告)日：2011-10-27

申请号：PCT/EP2010066149

申请日：2010-10-26

Applicant: IBM ,  MOUMEN NAIM ,  MARTIN YVES ,  VAN KESSEL THEODORE GERARD ,  SANDSTROM ROBERT ,  GUHA SUPRATIK

Inventor： MOUMEN NAIM ,  MARTIN YVES ,  VAN KESSEL THEODORE GERARD ,  SANDSTROM ROBERT ,  GUHA SUPRATIK

IPC: H01L31/0224 ,  H01L31/068

CPC classification number: H01L31/1804 ,  H01L31/02245 ,  H01L31/0682 ,  Y02E10/547 ,  Y02P70/521

Abstract: Electrical contact to the front side of a photovoltaic cell is provided by an array of conductive through-substrate vias, and optionally, an array of conductive blocks located on the front side of the photovoltaic cell. A dielectric liner provides electrical isolation of each conductive through-substrate via from the semiconductor material of the photovoltaic cell. A dielectric layer on the backside of the photovoltaic cell is patterned to cover a contiguous region including all of the conductive through-substrate vias, while exposing a portion of the backside of the photovoltaic cell. A conductive material layer is deposited on the back surface of the photovoltaic cell, and is patterned to form a first conductive wiring structure that electrically connects the conductive through-substrate vias and a second conductive wiring structure that provides electrical connection to the backside of the photovoltaic cell.

Abstract translation: 到光伏电池正面的电接触由导电的直通基板通孔阵列提供，并且可选地，位于光伏电池正面上的导电块阵列提供。 电介质衬垫提供每个导电贯穿衬底通孔与光伏电池的半导体材料的电隔离。 在光伏电池的背面上的电介质层被图案化以覆盖包括所有导电的贯穿衬底通孔的连续区域，同时暴露光伏电池的背面的一部分。 导电材料层被沉积在光伏电池的后表面上，并且被图案化以形成第一导电布线结构，其电连接导电贯穿基板通孔和第二导电布线结构，该第二导电布线结构提供到光伏电池的后侧的电连接 细胞。

公开(公告)号：WO2008088669A8

公开(公告)日：2009-02-05

申请号：PCT/US2008000006

申请日：2008-01-02

Applicant: IBM ,  APPENZELLER JOERG ,  GUHA SUPRATIK ,  TUTUC EMANUEL

Inventor： APPENZELLER JOERG ,  GUHA SUPRATIK ,  TUTUC EMANUEL

IPC: H01L29/06 ,  B82B1/00 ,  B82B3/00

CPC classification number: H01L21/30604 ,  B82Y10/00 ,  H01L21/02603 ,  H01L29/0665 ,  H01L29/0673 ,  H01L29/068 ,  H01L29/1041 ,  H01L29/125 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/78696

Abstract: A semiconductor structure is provided, which includes multiple sections arranged along a longitudinal axis. Preferably, the semiconductor structure comprises a middle section and two terminal sections located at opposite ends of the middle section. A semiconductor core having a first dopant concentration preferably extends along the longitudinal axis through the middle section and the two terminal sections. A semiconductor shell having a second, higher dopant concentration preferably encircles a portion of the semiconductor core at the two terminal sections, but not at the middle section, of the semiconductor structure. It is particularly preferred that the semiconductor structure is a nanostructure having a cross-sectional dimension of not more than 100 nm.

Abstract translation: 提供了一种半导体结构，其包括沿纵向轴线布置的多个部分。 优选地，半导体结构包括位于中间部分的相对端的中间部分和两个端子部分。 具有第一掺杂剂浓度的半导体芯片优选地沿着纵向轴线延伸通过中间部分和两个端子部分。 具有第二较高掺杂剂浓度的半导体壳体优选地环绕半导体结构的两个端子部分但不在中间部分处的半导体芯体的一部分。 特别优选的是，半导体结构是具有不大于100nm的横截面尺寸的纳米结构。

公开(公告)号：WO2006055226A3

公开(公告)日：2007-08-23

申请号：PCT/US2005039288

申请日：2005-11-01

Applicant: IBM ,  BOJARCZUK NESTOR A JR ,  CABRAL CYRIL JR ,  CARTIER EDUARD A ,  FRANK MARTIN M ,  GOUSEV EVGENI P ,  GUHA SUPRATIK ,  JAMISON PAUL C ,  JAMMY RAJARAO ,  NARAYANAN VIJAY ,  PARUCHURI VAMSI K

Inventor： BOJARCZUK NESTOR A JR ,  CABRAL CYRIL JR ,  CARTIER EDUARD A ,  FRANK MARTIN M ,  GOUSEV EVGENI P ,  GUHA SUPRATIK ,  JAMISON PAUL C ,  JAMMY RAJARAO ,  NARAYANAN VIJAY ,  PARUCHURI VAMSI K

IPC: H01L29/792 ,  H01L21/336 ,  H01L29/76 ,  H01L29/94 ,  H01L31/00

CPC classification number: H01L29/513 ,  H01L21/28194 ,  H01L21/2822 ,  H01L21/823828 ,  H01L21/823857 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/4975 ,  H01L29/517 ,  H01L29/518

Abstract: A semiconductor structure is provided that includes a V t stabilization layer between a gate dielectric and a gate electrode. The V t stabilization layer is capable of stabilizing the structure's threshold voltage and flatband voltage to a targeted value and comprises a nitrided metal oxide, or a nitrogen-free metal oxide, with the provision that when the V t stabilization layer comprises a nitrogen-free metal oxide, at least one of the semiconductor substrate or the gate dielectric includes nitrogen. The present invention also provides a method of fabricating such a structure.

Abstract translation: 提供了一种半导体结构，其包括在栅极电介质和栅电极之间的V 1稳定层。 VST稳定层能够将结构的阈值电压和平带电压稳定到目标值，并且包括氮化金属氧化物或无氮金属氧化物，其条件是当V < 稳定层包括无氮金属氧化物，半导体衬底或栅极电介质中的至少一个包括氮。 本发明还提供一种制造这种结构的方法。

公开(公告)号：DE112018003101B4

公开(公告)日：2021-11-11

申请号：DE112018003101

申请日：2018-08-02

Applicant: IBM

Inventor： VAN KESSEL THEODORE ,  CHANG JOSEPHINE ,  HAMANN HENDRIK ,  GERSHON TALIA SIMCHA ,  GUHA SUPRATIK ,  LIU JIAXING

IPC: G01N25/32 ,  G01N27/00

Abstract: Sensor für feuergefährliche Gase, aufweisend:mindestens eine erste Elektrode;mindestens eine zweite Elektrode, die aus einem Material gebildet ist, das ungleich dem der ersten Elektrode ist;ein inertes Substrat, an dem die mindestens eine erste Elektrode und die mindestens eine zweite Elektrode befestigt sind, wobei die mindestens eine erste Elektrode und die mindestens eine zweite Elektrode jeweils als Streifen eingerichtet sind, die rechtwinklig zueinander auf dem Substrat angeordnet sind; undein katalytisches Material an einer aktiven Reaktionsverbindungsstelle zwischen der mindestens einen ersten Elektrode und der mindestens einen zweiten Elektrode, wo sich die Streifen kreuzen, wobei die aktive Reaktionsverbindungsstelle zwischen der mindestens einen ersten Elektrode und der mindestens einen zweiten Elektrode ein Thermoelement bildet.

公开(公告)号：DE112010004353B4

公开(公告)日：2015-10-22

申请号：DE112010004353

申请日：2010-10-18

Applicant: IBM

Inventor： VAN KESSEL THEODORE GERARD ,  GUHA SUPRATIK ,  MARTIN YVES C ,  SANDSTROM ROBERT L

IPC: G01N25/72

Abstract: Verfahren zum Analysieren von Solarzellenplatten im praktischen Betrieb unter Verwendung eines von einer Infrarotkamera aufgenommenen Infrarotwärmebildes der Solarzellenplatten im Betrieb, wobei das Verfahren die folgenden Schritte umfasst: Aussetzen der Solarzellenplatte der Sonnenstrahlung; Umwandeln des Infrarotwärmebildes in Temperaturdaten; Isolieren einzelner Elemente durch Identifizieren von rechteckigen Bereichen des Infrarotwärmebildes, die Solarzellenplatten in dem Infrarotwärmebild entsprechen; tabellarisches Anordnen der Temperaturdaten für jedes isolierte Element; Ermitteln eines Leistungsfähigkeitsstatus jedes isolierten Elements auf der Grundlage der tabellarisch angeordneten Temperaturdaten; und Erzeugen eines Berichtes über den Leistungsfähigkeitsstatus jedes der isolierten Elemente, wobei ein Wärmemodell auf die Solarzellenplatte angewendet wird, das mindestens eines von einem Wärmewiderstand der Solarzellenplatte, einer Ausrichtung der Solarzellenplatte, einer Windgeschwindigkeit und einer Sonneneinstrahlung berücksichtigt.