公开(公告)号：GB2511445A

公开(公告)日：2014-09-03

申请号：GB201408705

申请日：2012-12-24

Applicant: IBM

Inventor： BRYANT ANDRES ,  BASKER VEERARAGHAVAN S ,  BU HUIMING ,  LEOBANDUNG EFFENDI ,  HAENSCH WILFRIED ,  LIN CHUNG-HSUN ,  STANDAERT THEORDORUS E ,  YAMASHITA TENKO ,  YEH CHUN-CHEN

IPC: H01L29/417 ,  H01L29/66

Abstract: A method is provided for fabricating a finFET device. Fin structures are formed over a BOX layer. The fin structures include a semiconductor layer and extend in a first direction. A gate stack is formed on the BOX layer over the fin structures and extending in a second direction. The gate stack includes a high-K dielectric layer and a metal gate. Gate spacers are formed on sidewalls of the gate stack, and an epi layer is deposited to merge the fin structures. Ions are implanted to form source and drain regions, and dummy spacers are formed on sidewalls of the gate spacers. The dummy spacers are used as a mask to recess or completely remove an exposed portion of the epi layer. Silicidation forms silicide regions that abut the source and drain regions and each include a vertical portion located on the vertical sidewall of the source or drain region.

公开(公告)号：DE602004003967D1

公开(公告)日：2007-02-08

申请号：DE602004003967

申请日：2004-08-11

Applicant: IBM

Inventor： DENNARD ROBERT ,  HAENSCH WILFRIED ,  HANAFI HUSSEIN

IPC: H01L21/00 ,  H01L21/336 ,  H01L21/762 ,  H01L29/786

Abstract: provides SOI CMOS technology whereby a polysilicon back-gate is used to control the threshold voltage of the front-gate device, and the nMOS and pMOS back-gates are switched independently of each other and the front gates. Specifically, the present invention provides a method of fabricating a back-gated fully depleted CMOS device in which the device's back-gate is self-aligned to the device's front-gate as well as the source/drain extension. Such a structure minimizes the capacitance, while enhancing the device and circuit performance. The back-gated fully depleted CMOS device of the present invention is fabricated using existing SIMOX (separation by ion implantation of oxygen) or bonded SOI wafer bonding and thinning, polySi etching, low-pressure chemical vapor deposition and chemical-mechanical polishing.

公开(公告)号：AT349773T

公开(公告)日：2007-01-15

申请号：AT04766475

申请日：2004-08-11

Applicant: IBM

Inventor： DENNARD ROBERT ,  HAENSCH WILFRIED ,  HANAFI HUSSEIN

IPC: H01L21/336 ,  H01L21/762 ,  H01L29/786 ,  H01L21/00

Abstract: provides SOI CMOS technology whereby a polysilicon back-gate is used to control the threshold voltage of the front-gate device, and the nMOS and pMOS back-gates are switched independently of each other and the front gates. Specifically, the present invention provides a method of fabricating a back-gated fully depleted CMOS device in which the device's back-gate is self-aligned to the device's front-gate as well as the source/drain extension. Such a structure minimizes the capacitance, while enhancing the device and circuit performance. The back-gated fully depleted CMOS device of the present invention is fabricated using existing SIMOX (separation by ion implantation of oxygen) or bonded SOI wafer bonding and thinning, polySi etching, low-pressure chemical vapor deposition and chemical-mechanical polishing.