公开(公告)号：CA1335843C

公开(公告)日：1995-06-06

申请号：CA557756

申请日：1988-01-29

Applicant: IBM

Inventor： HEATH CHESTER A ,  LANGGOOD JOHN K ,  VALLI RONALD E

IPC: G06F13/14 ,  G06F1/00 ,  G06F1/18 ,  G06F1/24 ,  G06F9/44 ,  G06F9/445 ,  G06F11/22 ,  G06F12/06 ,  G06F15/177 ,  G06K17/00 ,  G06F12/00 ,  G06F13/00

Abstract: A data processing system includes a planar board having a central processing unit (CPU), a main memory unit, and input/output (I/O) sockets or slots, each adapted to receive a selected one of a plurality of different and/or similar option cards. Each card contains (or is connected to) and controls a respective peripheral device; and each card is pre-wired with an ID value corresponding to its card type. Software programmable option registers on each card store parameters such as designated default (or alternate) address information, priority levels, and other system resource parameters. A setup routine, during initial power-on, retrieves and stores the appropriate parameters in the I/O cards and also in slot positions in main memory, one position being assigned to each slot on the board. Each slot position is adapted to hold the parameters associated with the card inserted in its respective slot and the card ID value. That portion of main memory containing the slot positions is adapted to maintain the parameter and ID information by means of battery power when system power fails or is disconnected, i.e., a nonvolatile memory portion. Subsequent power-on routines are simplified by merely transferring parameters from the table to the card option registers if the status of all the slots has not not changed since the last power-down, system reset, or channel reset.

公开(公告)号：CA1299295C

公开(公告)日：1992-04-21

申请号：CA557758

申请日：1988-01-29

Applicant: IBM

Inventor： CONCILIO IAN A ,  HAWTHORNE JEFFREY A ,  HEATH CHESTER A ,  LENTA JORGE E ,  NGUYEN LONG D

IPC: G06F13/28 ,  G06F13/30 ,  G06F13/36 ,  G06F13/362 ,  G06F13/374

Abstract: IBM Docket No. BC9-87-001 DMA ACCESS ARBITRATION DEVICE IN WHICH CPU CAN ARBITRATE ON BEHALF OF ATTACHMENT HAVING NO ARBITER In a computer system having both peripherals having their own DMA channel arbiter and peripherals having no arbiter, a separate arbitration unit, controlled directly by the CPU, is provided to arbitrate on behalf of peripherals having no arbiter. The CPU can thus freely assign different arbitration levels to such peripherals, and can instruct the arbitration unit to simultaneously arbitrate on different arbitration levels or for two or more DMA channels.

公开(公告)号：BR8800739A

公开(公告)日：1988-10-04

申请号：BR8800739

申请日：1988-02-23

Applicant: IBM

Inventor： CONCILIO IAN A ,  HAWTHORNE JEFFREY A ,  HEATH CHESTER A ,  LENTA JORGE E ,  NGUYEN LONG D

IPC: G06F13/28 ,  G06F13/30 ,  G06F13/36 ,  G06F13/362 ,  G06F13/374 ,  G06F13/40

Abstract: A computer system is coupled to peripherals having their own DMA channel arbiter and peripherals having no arbiter. A separate arbitration unit, controlled directly by the CPU, is provided to arbitrate on behalf of peripherals having no arbiter. The CPU can thus freely assign different arbitration levels to such peripherals, and can instruct the arbitration unit to simultaneously arbitrate on different arbitration levels or for two or more DMA channels.

公开(公告)号：IT8819553D0

公开(公告)日：1988-02-26

申请号：IT1955388

申请日：1988-02-26

Applicant: IBM

Inventor： HEATH CHESTER A ,  LANGGOOD JOHN K ,  VALLI RONALD E

IPC: G06F1/00 ,  G06F13/14 ,  G06F1/18 ,  G06F1/24 ,  G06F9/44 ,  G06F9/445 ,  G06F11/22 ,  G06F12/06 ,  G06F15/177 ,  G06K17/00 ,  G06F

Abstract: A data processing system includes a central processing unit (CPU), a main memory unit, and input/output (I/O) sockets, each adapted to receive a selected one of a plurality of different and/or similar option cards. Each card contains (or is connected to) and controls a respective peripheral device, and each card is pre-wired with an ID value corresponding to its card type. Programmable option registers on each card store parameters such as address information, priority levels, and other system resource parameters. A setup routine, during initial power-on, retrieves and stores the appropriate parameters in the I/O cards and also in socket locations in main memory, one location being assigned to each input/output socket. Each socket location is adapted to hold the parameters associated with the card inserted in its respective socket and the card ID value. That portion of main memory containing the socket locations is adapted to maintain the parameter and ID information by means of battery power when system power fails or is disconnected, i.e., a non-volatile memory portion. Subsequent power-on routines are simplified by merely transferring parameters from the memory to the card registers if the status of all the sockets has not changed since the last power-down.

公开(公告)号：IT1165427B

公开(公告)日：1987-04-22

申请号：IT2812279

申请日：1979-12-18

Applicant: IBM

Inventor： HEATH CHESTER A

IPC: G06F5/06 ,  G06F5/10 ,  G06F

Abstract: A data buffer system is provided for controlling the transfer of data between a processor and an input/output (I/O) device and includes a data storage device having a maximum data storage capacity value. The data storage device is disposed between the processor and the I/O device for receiving data input from the processor and for outputting data to the I/O device to thereby transfer data from the processor to the I/O device. The data storage device temporarily stores a predetermined amount of data while simultaneously transferring data between the processor and the I/O device. Circuitry is provided for selectively establishing a threshold storage capacity value of the data storage device wherein the threshold storage capacity value is less than the maximum storage capacity value of the data storage device. Circuitry is further provided for maintaining the predetermined amount of data temporarily stored in the data storage device equal to the threshold storage capacity value while the data storage device receives data from the processor and outputs data to the I/O device.

公开(公告)号：AU1078483A

公开(公告)日：1983-08-11

申请号：AU1078483

申请日：1983-01-26

Applicant: IBM

Inventor： ANDREWS LAWRENCE P ,  HEATH CHESTER A ,  MEAD JUSTIN E ,  DUREN RICHARD G VAN ,  JANES GARY A

IPC: G06F13/12 ,  G06F13/38 ,  G06F13/40 ,  G06F13/42 ,  G06F3/00 ,  G06F13/00

Abstract: This I/O interface permits attachment of a data processing system to devices having different "handshaking" protocols and bit-parallel data exchange capacities. Handshaking control circuits permit the system to communicate with devices variously in pulsed and interlocked modes. Timer circuits provide a variety of different time reference signals for transfer to devices. Switching options associated with the timer permit selective use of timer outputs as pulsed mode handshaking functions. A counter circuit and associated interface port permit the system to count events associated with device-originated pulses. A switching option permits the counter incrementing operations to be governed by timer outputs. The interface also contains path selection lines. In one mode these lines define high speed exchange of data between a primary system processor and devices in various bit-parallel formats and over various buses designatable by a systems processor. In another mode these lines permit a secondary system processor to exchange data with a series of multiplexed devices. Collectively, the interface lines have a symmetrical configuration which permits their use for direct interconnection of two data processing systems without the expense of additional "channel to channel" adaptation.

公开(公告)号：CA1290069C

公开(公告)日：1991-10-01

申请号：CA558104

申请日：1988-02-04

Applicant: IBM

Inventor： HEATH CHESTER A ,  JACKSON KEVIN M ,  JUDICE DARRYL E ,  PESTONJI HOSHANG R

IPC: G06F9/48 ,  G06F9/46 ,  G06F13/24 ,  G06F15/78

Abstract: A personal computer system with associated interrupt controller is preferably designed to operate with programs and respond to interrupt related commands in one mode, such as level sensitive mode, but is provided with circuitry that enables the system to convert and respond to interrupt related software commands in another mode, such as edge sensitive (triggered) mode, the system there treating the edge mode signals just as if they were level mode signals. BC9-86-006

公开(公告)号：BR8800736A

公开(公告)日：1988-10-11

申请号：BR8800736

申请日：1988-02-23

Applicant: IBM

Inventor： HEATH CHESTER A ,  JACKSON KEVIN M ,  JUDICE DARRYL E ,  PESTONJI HOSHANG R

IPC: G06F9/48 ,  G06F9/46 ,  G06F13/24 ,  G06F15/78 ,  G06F13/26

Abstract: A personal computer system with associated interrupt controller is preferably designed to operate with programs and respond to interrupt related commands in one mode, such as level sensitive mode, but is provided with circuitry that enables the system to convert and respond to interrupt-related software commands in another mode, such as edge sensitive (triggered) mode, the system then treating the edge mode signals just as if they were level mode signals.

公开(公告)号：CA1184311A

公开(公告)日：1985-03-19

申请号：CA419312

申请日：1983-01-12

Applicant: IBM

Inventor： HEATH CHESTER A

IPC: G06F13/12 ,  G06F13/36 ,  G06F13/38 ,  G06F13/40 ,  G06F13/42 ,  G06F17/21 ,  G06F3/00 ,  G06F13/00

Abstract: PERIPHERAL INTERFACE ADAPTER CIRCUIT FOR USE IN I/O CONTROLLER CARD HAVING MULTIPLE MODES OF OPERATION This adapter contains two separately controllable sections, each transferring data in various formats between a peripheral device interface and either a microprocessor contained in an associated I/O controller or a host processor or both. Dedicated controls enable the adapter to operate autonomously after being prepared by the microprocessor. Separate but interconnectable handshaking controls enable the sections to operate either asynchronously or in time coordination with each other. Handshaking controls in plural adapters are interconnectable to coordinate related transfers of data between a device and one or more hosts via plural adapter paths. Programmable commands enable the microprocessor to condition the adapter to conduct various data transfers autonomously. Such data can be transferred to or from the device interface in various bit-parallel formats defined by the commands, and from or to the host processor, the microprocessor, or both the host processor and microprocessor concurrently. In one handshaking mode, the adapter sustains an array indexing operation in which one section transfers "address" data to a device and the other section transfers "addressed" portions of a data array between the same device and either the host processor or the microprocessor.

公开(公告)号：CA1182577A

公开(公告)日：1985-02-12

申请号：CA419296

申请日：1983-01-12

Applicant: IBM

Inventor： HEATH CHESTER A ,  VAN DUREN RICHARD G

IPC: G06F15/16 ,  G06F13/00 ,  G06F13/12 ,  G06F13/28 ,  G06F15/17 ,  G06F15/177

Abstract: CYCLE STEALING I/O CONTROLLER WITH PROGRAMMABLE OFFLINE MODE OF OPERATION A dual mode microprocessor acts either as a front-end I/O controller processor relative to a primary/ host processor and device or as a secondary data processor having independent storage, processing and I/O capabilities. Host software prepares device control block (DCB) arrays, which contain primary commands interpretable by the microprocessor and evoke these modes. Each DCB contains a chaining bit permitting its interpretation sequence to be chained (or not chained) to another DCB sequence, and a mode bit defining either a high speed DI/DO (HS) mode of operation or a programmable offline (PO) mode. In HS mode the microprocessor conditions associated adapters to transfer a specified amount of data between the host memory and device, through a specified interface busing path and in a specified bit-parallel format. The adapters perform this transfer in an autonomous manner, i.e., without assistance from either processor. In PO mode the microprocessor directs associated elements to perform one or more programs of operations defined by secondary commands contained in a command list. Such lists, prepared in advance in host system memory, are transferred to the microprocessor's memory by special PO mode "LOAD" type DCB's, and interpreted in response to special PO mode type "START" DCB's. A list transferred by one LOAD DCB may be repeatedly accessed at various positions by several START DCB's. The architecture of the command list includes commands which permit the microprocessor to exchange data with the host and/or a device, perform arithmetic operations on data, perform bit and byte manipulative operations on data, and directly control the device interface. PO mode sequences are terminatable by the microprocessor in response to various internal and external conditions. Upon termination the microprocessor evokes either a DCB chaining action or a host system interruption for transferring concluding status, depending on the value of the chaining bit in the current (start type) DCB.