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    11.
    发明专利
    未知

    公开(公告)号：NO880605L

    公开(公告)日：1988-09-14

    申请号：NO880605

    申请日：1988-02-11

    Applicant: IBM

    Inventor： HEATH CHESTER ASBURY ,  LANGGOOD JOHN KENNEDY ,  VALLI RONALD EUGENE

    IPC: G06F1/00 ,  G06F13/14 ,  G06F1/18 ,  G06F1/24 ,  G06F9/44 ,  G06F9/445 ,  G06F11/22 ,  G06F12/06 ,  G06F15/177 ,  G06K17/00 ,  G06F13/00

    Abstract: A data processing system includes a central processing unit (CPU), a main memory unit, and input/output (I/O) sockets, each adapted to receive a selected one of a plurality of different and/or similar option cards. Each card contains (or is connected to) and controls a respective peripheral device, and each card is pre-wired with an ID value corresponding to its card type. Programmable option registers on each card store parameters such as address information, priority levels, and other system resource parameters. A setup routine, during initial power-on, retrieves and stores the appropriate parameters in the I/O cards and also in socket locations in main memory, one location being assigned to each input/output socket. Each socket location is adapted to hold the parameters associated with the card inserted in its respective socket and the card ID value. That portion of main memory containing the socket locations is adapted to maintain the parameter and ID information by means of battery power when system power fails or is disconnected, i.e., a non-volatile memory portion. Subsequent power-on routines are simplified by merely transferring parameters from the memory to the card registers if the status of all the sockets has not changed since the last power-down.

    13.
    发明专利
    未知

    公开(公告)号：FI93585B

    公开(公告)日：1995-01-13

    申请号：FI880656

    申请日：1988-02-12

    Applicant: IBM

    Inventor： HEATH CHESTER ASBURY ,  LANGGOOD JOHN KENNEDY ,  VALLI RONALD EUGENE

    IPC: G06F1/00 ,  G06F1/18 ,  G06F13/14 ,  G06F1/24 ,  G06F9/44 ,  G06F9/445 ,  G06F11/22 ,  G06F12/06 ,  G06F15/177 ,  G06K17/00

    Abstract: A data processing system includes a central processing unit (CPU), a main memory unit, and input/output (I/O) sockets, each adapted to receive a selected one of a plurality of different and/or similar option cards. Each card contains (or is connected to) and controls a respective peripheral device, and each card is pre-wired with an ID value corresponding to its card type. Programmable option registers on each card store parameters such as address information, priority levels, and other system resource parameters. A setup routine, during initial power-on, retrieves and stores the appropriate parameters in the I/O cards and also in socket locations in main memory, one location being assigned to each input/output socket. Each socket location is adapted to hold the parameters associated with the card inserted in its respective socket and the card ID value. That portion of main memory containing the socket locations is adapted to maintain the parameter and ID information by means of battery power when system power fails or is disconnected, i.e., a non-volatile memory portion. Subsequent power-on routines are simplified by merely transferring parameters from the memory to the card registers if the status of all the sockets has not changed since the last power-down.

    15.
    发明专利
    未知

    公开(公告)号：AT81220T

    公开(公告)日：1992-10-15

    申请号：AT87118545

    申请日：1987-12-15

    Applicant: IBM

    Inventor： HEATH CHESTER ASBURY ,  LENTA JORGE EDUARDO

    IPC: G06F13/28 ,  G06F13/30 ,  G06F13/36 ,  G06F13/362 ,  G06F13/374

    Abstract: A computer system in which peripherals greater in number than the number of DMA channels provided in the system can all have DMA access. Some of the DMA channels are dedicated to certain ones of the peripherals, while others are shared by remaining ones of the peripherals. Each peripheral having DMA access has a channel priority value. When a peripheral wants DMA access, it transmits its channel priority value onto an arbitration bus. The winning channel priority value is then compared with prestored DMA channel assignment values. If the comparison is successful, the corresponding peripheral is given a DMA channel corresponding to the DMA channel assignment value with which the comparison was successful.

    17.
    发明专利
    未知

    公开(公告)号：DE3778010D1

    公开(公告)日：1992-05-07

    申请号：DE3778010

    申请日：1987-12-15

    Applicant: IBM

    Inventor： HEATH CHESTER ASBURY ,  JACKSON KEVIN MICHAEL ,  JUDICE DARRYL EDMOND ,  PESTONJI HOSHANG RATAN

    IPC: G06F9/48 ,  G06F9/46 ,  G06F13/24 ,  G06F15/78

    Abstract: A personal computer system with associated interrupt controller is preferably designed to operate with programs and respond to interrupt related commands in one mode, such as level sensitive mode, but is provided with circuitry that enables the system to convert and respond to interrupt-related software commands in another mode, such as edge sensitive (triggered) mode, the system then treating the edge mode signals just as if they were level mode signals.

    18.
    发明专利
    未知

    公开(公告)号：AT74455T

    公开(公告)日：1992-04-15

    申请号：AT87118543

    申请日：1987-12-15

    Applicant: IBM

    Inventor： HEATH CHESTER ASBURY ,  JACKSON KEVIN MICHAEL ,  JUDICE DARRYL EDMOND ,  PESTONJI HOSHANG RATAN

    IPC: G06F9/48 ,  G06F9/46 ,  G06F13/24 ,  G06F15/78

    Abstract: A personal computer system with associated interrupt controller is preferably designed to operate with programs and respond to interrupt related commands in one mode, such as level sensitive mode, but is provided with circuitry that enables the system to convert and respond to interrupt-related software commands in another mode, such as edge sensitive (triggered) mode, the system then treating the edge mode signals just as if they were level mode signals.

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