公开(公告)号：JPH0684358A

公开(公告)日：1994-03-25

申请号：JP560493

申请日：1993-01-18

Applicant: IBM

Inventor： SAN HOO DON ,  KITAMURA TSUNEJI ,  KIRIHATA TOSHIAKI ,  SUNANAGA TOSHIO

IPC: G11C11/409 ,  G11C7/06 ,  G11C11/407 ,  G11C11/4091

Abstract: PURPOSE: To reduce the swing of a bit line by limiting the swing of a rise bit line to prescribed voltage higher than power voltage. CONSTITUTION: External voltages VCC and VSS are used for a word line driver 20, PMOS cell array 16 in an n-type well, a COMS AC connection sense amplifier 18 and a bit line monitor circuit 22. Since an initial bit line is precharged by VEQ which is larger than the threshold of QPCELL of VTP, a signal can be generated at high speed. A signal charge appearing on the bit line BL30 from an access cell is speedily detected in the sense amplifier at sense clocks ϕSR and ϕSP. Here, voltages VCC and VSS charge rise BL and discharge fall BL. Thus, sense speed improves. At that time, a reference bit is monitored in the monitor circuit 22, non-activates clocks ϕ1 and ϕ2 and limits voltage when it reaches setting voltage. Then, the swing of boosting voltage is limited between a power source and setting voltage and the swing of the bit line can be reduced.

公开(公告)号：JP2004127463A

公开(公告)日：2004-04-22

申请号：JP2002293309

申请日：2002-10-07

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： MIYATAKE HISATADA ,  UMEZAKI HIROSHI ,  KITAMURA TSUNEJI ,  SUNANAGA TOSHIO ,  NODA HIROYOSHI ,  ASANO HIDEO

IPC: G11C11/15 ,  G11C29/02 ,  H01L21/8246 ,  H01L27/105 ,  H01L43/08

CPC classification number: G11C11/16 ,  G11C29/02 ,  G11C29/028 ,  G11C2029/5006

Abstract: PROBLEM TO BE SOLVED: To provide a method for determining an optimum write bit line current and an optimum write word line current in an MRAM.
SOLUTION: In an asteroid curve represented by a bit line magnetic field H
x generated by a write bit line current I
B and a word line magnetic field H
y generated by a write word line current I
W , manufacturing variations and a design margin are taken into consideration to assume an asteroid curve AC
out outside all memory cell asteroid curves (located with a hatched area of Figure). The write bit line current and write word line current are selected so as to minimize write electric power consumed by a write current obtained by totalizing the write bit line current and the write word line current or a bit line and a write word line. In addition, a write bit line current and a write word line current are selected so as to form a synthetic magnetic field on a curve between a point H1 and a point H2 on the asteroid curve AC
out in order to prevent multi-selection.
COPYRIGHT: (C)2004,JPO

公开(公告)号：JP2004088597A

公开(公告)日：2004-03-18

申请号：JP2002248936

申请日：2002-08-28

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： SUNANAGA TOSHIO ,  MIYATAKE HISATADA ,  KITAMURA TSUNEJI

IPC: H01L21/82 ,  G06F15/78 ,  H01L21/8246 ,  H01L27/10 ,  H01L27/105 ,  H03K19/173 ,  H03K19/177

CPC classification number: G06F15/7867

Abstract: PROBLEM TO BE SOLVED: To provide a field programmable gate array (FPGA) which can shorten a configuration time and a time for rewriting wiring information and logic arrangement information, and can reduce its occupation area.
SOLUTION: For storing FPGA wiring information, magnetic memory elements MTJ1 to MTJn are provided as MRAM memory cells. A shift register 71 is used to input the wiring information to the magnetic memory elements MTJ1 to MTJn. The register 71 includes register elements SR1 to SRn corresponding to the magnetic memory elements MTJ1 to MTJn. The wiring information are serially input to the register elements SR1 to SRn and stored therein. When the power is turned on, the wiring information of the magnetic memory elements MTJ1 to MTJn are latched by latch elements LT1 to LTn and output to a switch circuit 6 for interconnecting logic blocks.
COPYRIGHT: (C)2004,JPO

公开(公告)号：JP2003198354A

公开(公告)日：2003-07-11

申请号：JP2001382556

申请日：2001-12-17

Applicant: IBM

Inventor： MIYATAKE HISATADA ,  SUNANAGA TOSHIO ,  KITAMURA TSUNEJI

IPC: G11C11/14 ,  G11C11/15 ,  H01L21/8246 ,  H01L27/105 ,  H01L43/08 ,  H03K19/00

Abstract: PROBLEM TO BE SOLVED: To retain a latch status in a logic circuit which is on stand by status without losing original features in the logic circuit which achieves low electric power consumption and high speed performance using a MTCMOS circuit. SOLUTION: Power source lines Vdd and Vss, and virtual power source lines v-Vdd and v-Vss are connected with MOSFETHvt-Tr1 and Hvt-Tr2 which have high threshold voltage. Power source is supplied from v-Vdd and v-Vss to the combinational logic circuit 1 and nonvolatile latch circuits NVL1 to n. NVL1 to n are connected to arbitrary nodes which require status report on the stand by status in the combinational logic circuit 1. COPYRIGHT: (C)2003,JPO

公开(公告)号：JP2003157671A

公开(公告)日：2003-05-30

申请号：JP2001358222

申请日：2001-11-22

Applicant: IBM

Inventor： MIYATAKE HISATADA ,  SUNANAGA TOSHIO ,  KITAMURA TSUNEJI

IPC: G11C11/14 ,  G11C11/15 ,  H03K3/356

Abstract: PROBLEM TO BE SOLVED: To provide a nonvolatile latch circuit in which nonvolatile memory elements are individually arranged within a logic circuit. SOLUTION: Tunnel magneto resistive elements MTJ0 and MTJ1 are connected to the respective sources of inverters INV1 and INV2 having a C-MOS structure and output and input of the inverters INV1 and INV2 are mutually cross connected. Transistors Tr5 and Tr6 which are used for precharging are connected to the output of the inverters and a transistor Tr7 is arranged between the elements MTJ0 and MTJ1 and the ground. Data are written into the elements MTJ0 and MTJ1 by the current that is flowing in a data writing line DWL and the states recorded in the elements MTJ0 and MTJ1 are taken out to an output OUT and an output OUT bar by REFRESHN signals.

公开(公告)号：JP2003007080A

公开(公告)日：2003-01-10

申请号：JP2001185167

申请日：2001-06-19

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーション

Inventor： SUNANAGA TOSHIO ,  MIYATAKE HISATADA ,  KITAMURA TSUNEJI ,  ASANO HIDEO

IPC: H01L27/04 ,  G11C29/00 ,  G11C29/04 ,  H01L21/82 ,  H01L21/822

Abstract: PROBLEM TO BE SOLVED: To reduce a test cost by omitting a shifting process in which a chip on a wafer is shifted from a test device to a cutting device once to cut a fuse of a fuse circuit block in a conventional fuse circuit block. SOLUTION: This device is provided with two non-volatile storage elements 16, 18 storing data of connection or cut off of a fuse circuit, a circuit changing the direction of magnetization of this non-volatile storage elements 16, 18, and a current mirror circuit reading data stored in the non-volatile storage elements 16, 18.

Abstract translation: 要解决的问题：通过省略将晶片上的芯片从测试装置切换到切割装置一次以切断常规熔丝电路块中的熔丝电路块的熔丝的移位处理来降低测试成本。 解决方案：该设备设有两个非易失性存储元件16,18，其存储熔丝电路的连接或切断数据，改变该非易失性存储元件16,18和电流镜18的磁化方向的电路 存储在非易失性存储元件16,18中的电路读取数据。

公开(公告)号：JP2002368197A

公开(公告)日：2002-12-20

申请号：JP2001163655

申请日：2001-05-31

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーション

Inventor： KITAMURA TSUNEJI ,  SUNANAGA TOSHIO ,  MIYATAKE HISATADA ,  NAKAMURA TAKASHI

IPC: G11C11/14 ,  G11C11/15 ,  H01L21/8246 ,  H01L27/10 ,  H01L27/105 ,  H01L43/08

Abstract: PROBLEM TO BE SOLVED: To provide a nonvolatile magnetic memory cell and a storage circuit block employing the same. SOLUTION: A nonvolatile memory cell 32 includes a bit line 14; a storage element 10, including a ferromagnetic layer in which its magnetizing direction varies, depending on the direction of the magnetic field generated by a current flowing through the bit line 14; a conductor 12 for connecting the bit line 14 to the element 10, a switching element 28; a first wiring structure 24 sandwiching the element 10 between the conductors 12 and itself, and connecting the element 10 to one end of the element 28; a write work line 16 intersecting with the bit line 14 in a no-contact manner therewith; and an insulation film 20 for insulating the work line 16 from the element 10.

Abstract translation: 要解决的问题：提供一种非易失性磁性存储单元和使用其的存储电路块。 解决方案：非易失性存储单元32包括位线14; 存储元件10，其包括根据由流过位线14的电流产生的磁场的方向，其磁化方向变化的铁磁层; 用于将位线14连接到元件10的导体12，开关元件28; 将元件10夹在导体12和本身之间并将元件10连接到元件28的一端的第一布线结构24; 写入工作线16与位线14以不接触的方式相交; 以及用于将工作线16与元件10绝缘的绝缘膜20。

公开(公告)号：JP2002230965A

公开(公告)日：2002-08-16

申请号：JP2001015475

申请日：2001-01-24

Applicant: IBM

Inventor： ASANO HIDEO ,  SUNANAGA TOSHIO ,  KITAMURA TSUNEJI ,  MIYATAKE HISATADA ,  UMEZAKI HIROSHI ,  NODA HIROYOSHI

IPC: G11C11/14 ,  G11C11/15 ,  G11C11/16 ,  H01L21/8246 ,  H01L27/105 ,  H01L43/08

Abstract: PROBLEM TO BE SOLVED: To improve the reliability of recording of a MRAM. SOLUTION: This device has read-out word lines WLR and write-in word lines WLW extending in the direction of (y), and write-in read-out bit lines BLW/R and write-in bit lines BLW extending in the direction of (x), and a memory cell MC is arranged at an intersection of a word line and a bit line. The memory cell MC comprises a sub-cell SC1 and a sub-cell SC2, the sub-cell SC1 comprises magnetic resistance elements MTJ1, MTJ2, and a selection transistor Tr1, and the sub-cell SC2 comprises magnetic resistance elements MTJ3, MTJ4, and a selection transistor Tr2, and the sub-cell SC2, The magnetic resistance elements MTJ1 and MTJ2 are connected in parallel, also, the magnetic resistance elements MTJ3 and MTJ2 are connected in parallel. The sub- cells SC1 and SC2 are connected in series between the write-in read-out bit lines BLW/R and ground.

公开(公告)号：JPH08241963A

公开(公告)日：1996-09-17

申请号：JP2267895

申请日：1995-02-10

Applicant: IBM

Inventor： MIYATAKE HISATADA ,  SUNANAGA TOSHIO ,  KITAMURA TSUNEJI ,  YAMAMOTO MASAAKI

IPC: G11C11/401 ,  G11C5/14 ,  H01L21/8242 ,  H01L27/108

Abstract: PURPOSE: To provide a reliable high-density semiconductor integrated circuit device with high-speed operation by forming a DRAM macrocell and a logical cell in a common chip. CONSTITUTION: A DRAM macroscopic cell 14 is formed on the same cell as a logical cell. The DRAM macroscopic cell 14 includes a guard ring 26 of a conductive type opposite to that of a semiconductor substrate, a memory cell alley 42 formed in a well in the guard ring 26, a power line 34, a grounding line 36, and a bypass capacitor 70 joined between the power line 34 and the grounding line 36. The power line 36 and a logical-cell power line are connected to different power pads, while the grounding line 36 and a logic-cell grounding line are connected to a common grounding line or to grounding lines provided near to each other and connected with a low impedance line.