公开(公告)号：DE2457921C2

公开(公告)日：1976-12-09

申请号：DE2457921

申请日：1974-12-07

Applicant: IBM DEUTSCHLAND

Inventor： HEUBER KLAUS DIPL-ING ,  KLEIN WILFRIED ,  NAJMANN KNUT DIPL-ING ,  WIEDMANN SIEGFRIED DIPL-ING DR

IPC: G11C11/414 ,  G11C11/411 ,  G11C11/415

公开(公告)号：FR2304991A1

公开(公告)日：1976-10-15

申请号：FR7602996

申请日：1976-01-29

Applicant: IBM

Inventor： BERGER HORST ,  HEUBER KLAUS ,  KLEIN WILFRIED ,  NAJMANN KNUT

IPC: G11C11/414 ,  G11C11/411 ,  G11C11/416 ,  G11C11/40

Abstract: The invention relates to a circuit arrangement for operating the read/write cycles of an integrated semiconductor memory storage system whose storage cells consist of flip flops with bipolar switching transistors, Schottky diodes as read/write elements coupling the cell to the bit lines, and high-resistivity resistors, or transistors controlled as current sources, as load elements, in several phases.

公开(公告)号：FR2293766A1

公开(公告)日：1976-07-02

申请号：FR7532210

申请日：1975-10-13

Applicant: IBM

Inventor： HEUBER KLAUS ,  KLEIN WILFRIED ,  NAJMANN KNUT ,  WIEDMANN SIEGFRIED

IPC: G11C11/414 ,  G11C11/411 ,  G11C11/415 ,  G11C7/00 ,  G11C11/40

公开(公告)号：DE2460146A1

公开(公告)日：1976-06-24

申请号：DE2460146

申请日：1974-12-19

Applicant: IBM DEUTSCHLAND

Inventor： HEUBER KLAUS DIPL ING ,  KLEIN WILFRIED ,  NAJMANN KNUT DIPL ING ,  REMSHARDT ROLF DIPL ING DR ,  WIEDMANN SIEGFRIED DIPL ING DR

IPC: G11C11/41 ,  G11C11/34 ,  G11C11/416 ,  H03K3/287 ,  H03K5/02 ,  G11C7/00 ,  G11C11/40

Abstract: This teaches a sense circuit for an integrated memory storage system in which the storage cell output is detected by a differential amplifier, controlling a flip-flop, serving as a latch, having load elements which also function as the load elements of the latch to ensure an optimum power and speed product. The latch can be coupled to an output driver circuit through a current switch which shares common elements with the latch to assure that the latch remains symmetrical even when used with an output driver having asymmetrical control.

公开(公告)号：IT1149977B

公开(公告)日：1986-12-10

申请号：IT2271680

申请日：1980-06-11

Applicant: IBM

Inventor： HEIMER HELMUT H ,  KLEIN WILFRIED ,  NAJMANN KNUT ,  WERNICKE FRIEDERICH C

IPC: G11C11/41 ,  G11C7/02 ,  G11C7/06 ,  G11C7/20 ,  G11C11/24 ,  G11C11/34 ,  G11C11/40 ,  G11C11/4091 ,  G11C11/416

Abstract: An integrated semiconductor memory having memory cells which have (or are designed to have) inherent asymmetrical access times for the distinguishable memory states thereof. The memory is operated on the basis of the shorter access time. This is accomplished by utilizing an oppositely asymmetrical sense system, preferably in the form of a pre-set sense latch. For example, in the case of a digital memory with the reading of a "0" state having a shorter access time than the reading of a "1" state, at the beginning of a read operation a sense latch is set to the (slower) "1" state. Thus, only in the case of reading a "0" is the state of the latch changed to the "0" state. Thus, the actual access time is no longer determined by the longer access time, namely, the reading of a "1". The access time is determined by the shorter access time, namely, the reading of a "0". The concept may also be used if the sense latch has an asymmetric access time. Then it is advantageous to intentionally choose a corresponding asymetrical memory cell design.

公开(公告)号：DE2951945A1

公开(公告)日：1981-07-02

申请号：DE2951945

申请日：1979-12-22

Applicant: IBM DEUTSCHLAND

Inventor： BROSCH RUDOLF DIPL ING DR ,  HEIMEIER HELMUT DIPL ING DR ,  KLEIN WILFRIED ,  WERNICKE FRIEDRICH DIPL ING

IPC: G11C11/41 ,  G11C11/40 ,  G11C11/411 ,  G11C11/416 ,  G11C7/06

Abstract: After a controlled strong lowering of the word line potential for the purpose of addressing a cell, said potential is immediately recharged simultaneously increasing the potential on the N side of the two PNP injectors of the cell and causing the injector capacitances of the selected storage cells and the bit line capacitances to form a capacitive voltage divider, so that the bit lines connected thereto are recharged to different degrees by the different magnitudes of the injector capacitances. Thus, the differential signal formed on the bit lines is noticeably amplified by the supply of currents of different magnitudes.

公开(公告)号：DE2860462D1

公开(公告)日：1981-03-26

申请号：DE2860462

申请日：1978-06-19

Applicant: IBM

Inventor： KLEIN WILFRIED ,  KLINK ERICH DIPL ING ,  RUDOLPH VOLKER DIPL PHYS ,  WERNICKE FRIEDRICH DIPL ING

IPC: G11C11/41 ,  G11C11/40 ,  G11C11/414 ,  G11C11/416 ,  H01L21/822 ,  H01L21/8222 ,  H01L27/04 ,  H01L27/06 ,  H01L27/07 ,  H01L29/47 ,  H01L29/872

Abstract: The highly integrated semiconductor device is intended as a separating diode cooperating with selector lines of an integrated memory. The resistor (R) is of pinch-type whose pinch doping region (5) is greater than the cross sectional dimension of the resistor doping region (4). Simultaneously it forms a cathode connection doping region for the Schottky diode (D). Preferably the pinched doping region carries a connection contact (K) for the Schottky diode cathode terminal. This doped region is of identical conductivity as the surrounding semiconductor material (3), but of higher doping rate, sufficient to form an ohmic contact with a metal electrode on the region. On the resistance region (4) outside the pinch doping region is provided a metal contact (A), extending beyond the resistance region. -

公开(公告)号：FR2374725A1

公开(公告)日：1978-07-13

申请号：FR7733079

申请日：1977-10-24

Applicant: IBM

Inventor： HEUBER KLAUS ,  KLEIN WILFRIED ,  NAJMANN KNUT ,  WERNICKE FRIEDRICH ,  WIEDMANN SIEGFRIED K

IPC: G11C11/41 ,  G11C7/04 ,  G11C11/411 ,  G11C11/414 ,  G11C11/416 ,  G11C11/34 ,  G11C7/00

公开(公告)号：DE2556833A1

公开(公告)日：1977-06-30

申请号：DE2556833

申请日：1975-12-17

Applicant: IBM DEUTSCHLAND

Inventor： HEUBER KLAUS DIPL ING ,  KLEIN WILFRIED ,  NAJMANN KNUT DIPL ING ,  WIEDMANN SIEGFRIED DIPL ING DR

IPC: G11C11/41 ,  G11C11/411 ,  G11C11/414 ,  G11C11/415 ,  G11C7/00 ,  G11C11/40 ,  H01L29/76

Abstract: An improved method of operating a monolithic memory together with novel and efficient circuitry for practicing said improved method is disclosed. In a bipolar transistor store, or monolithic memory, in accordance with the invention, a very low current (first level) flows from the load elements to the internal cell nodes in the stand-by mode. During the initial portion of a read cycle, current flows from the bit lines to the cell nodes, in addition to the stand-by current (second level). In the recovery period of the read cycle or write cycle a short pulse is added to the stand-by current (third level), thereby reducing the recovery time. The practice of the invention provides a monolithic memory having minimal power requirements and a substantially reduced cycle time.

公开(公告)号：DE2511518A1

公开(公告)日：1976-09-16

申请号：DE2511518

申请日：1975-03-15

Applicant: IBM DEUTSCHLAND

Inventor： BERGER HORST DIPL ING DR ,  HEUBER KLAUS DIPL ING ,  KLEIN WILFRIED ,  NAJMANN KNUT DIPL ING ,  WIEDMANN SIEGFRIED DIPL ING DR

IPC: G11C11/414 ,  G11C11/411 ,  G11C11/416 ,  G11C7/00 ,  G11C11/40

Abstract: The invention relates to a circuit arrangement for operating the read/write cycles of an integrated semiconductor memory storage system whose storage cells consist of flip flops with bipolar switching transistors, Schottky diodes as read/write elements coupling the cell to the bit lines, and high-resistivity resistors, or transistors controlled as current sources, as load elements, in several phases.