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公开(公告)号：GB2515568A
公开(公告)日：2014-12-31
申请号：GB201311671
申请日：2013-06-28
Applicant: IBM
Inventor： ELEFTHERIOU EVANGELOS STAVROS , KREBS DANIEL , SEBASTIAN ABU
Abstract: Resistive random-access memory RRAM cells 10 are provided for storing information in a plurality of programmable cell states. An electrically-insulating matrix 11 is located between first electrodes 12 and second electrodes 3 such that an electrically-conductive path 14, can be formed within the matrix on application of a write voltage to the electrodes and which extends in a direction between the electrodes. The programmable cell states correspond to respective configurations of the conductive path in the matrix. An electrically conductive component 15 extends in a direction between the electrodes and is also in contact with the insulating matrix, and runs parallel with the electrically insulating matrix 11. The arrangement is such that the resistance presented by the electrically conductive component to a cell current produced by a read voltage, applied to the electrodes to read the programmed cell state, is at least that of the conductive path, and at most about that of the insulating matrix, in any of said cell states. The conductive component may form a sheath surrounding the electrically insulating matrix (figure 5), and may be tapered being narrower towards one of the electrodes (figure 14, 15). The conductive path may occupy at least 10% of the thickness of the insulating matrix perpendicular to a direction between the electrodes. The electrically insulating matrix may be elongate and may comprise of a nanowire. Another embodiment including a two state RRAM cell is included which are connected antiserially (Figure 19). Other embodiments use an annulus around a core member (figures 22 /23). A method of use is also included.
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Patent Agency Ranking
公开(公告)号：GB2502569A
公开(公告)日：2013-12-04
申请号：GB201209653
申请日：2012-05-31
Applicant: IBM
Inventor： KREBS DANIEL
Abstract: A method and apparatus are provided for programming gated phase-change memory cells 1, each with a gate G, source S and drain D, having two or more (s > or = 2) programmable cell-states including an amorphous RESET state and at least one crystalline state. A programming signal is applied between the source S and drain D of a memory cell 1 to program that cell to a desired cell-state. When programming a cell l from a crystalline state to the RESET state, a bias voltage 25 is applied to the gate of that cell to increase the cell resistance, providing an effective RESET current reduction. Cells may be read before programming to obtain an indication of cell-state. In this case, when programming a cell to the RESET state, the bias voltage can be applied only if a crystalline cell-state is indicated on reading. The bias voltage for the gate is set to increase the cell resistance to a value at or near a predetermined value for the crystalline state. When programming a cell to a crystalline state, zero bias is applied to the gate. The method relates to two level (single bit) and multi level (multi state, multi bit ) memory cells. Reading data is also described by applying a read signal between the source and drain of each cell with zero bias voltage applied to the gate of that cell, and making a read measurement to obtain an indication of the cell-state. Apparatus is described to enable the method to be executed. In the crystalline state, if the Fermi level is close to the conduction band, then application of a gate bias voltage G, 25 will move the Fermi level towards the valence band. Conversely if the Fermi level is close to the valence band in the crystalline state then application of the gate bias will move towards the conduction band (figures 4a, 4b).
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公开(公告)号：GB2486618A
公开(公告)日：2012-06-20
申请号：GB201206876
申请日：2010-11-10
Applicant: IBM
Inventor： BREITWISCH MATTHEW J , LAM CHUNG H , RAJENDRAN BIPIN , RAOUX SIMONE , SCHROTT ALEJANDRO G , KREBS DANIEL
Abstract: A phase change memory cell that includes a bottom electrode, a top electrode separated from the bottom electrode, and growth-dominated phase change material deposited between the bottom electrode and the top electrode and contacting the bottom electrode and the top electrode and surrounded by insulation material at sidewalls thereof. The phase change memory cell in a reset state only includes an amorphous phase of the growth-dominated phase change material within an active volume of the phase change memory cell.
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公开(公告)号：DE102014108256A1
公开(公告)日：2014-12-18
申请号：DE102014108256
申请日：2014-06-12
Applicant: IBM
Inventor： SEBASTIAN ABU , KREBS DANIEL
Abstract: Es werden Phasenänderungs-Speicherzellen 20, 40, 80, 90 zum Speichern von Daten in einer Vielzahl programmierbarer Zellzustände bereitgestellt. Ein Phasenänderungsmaterial 21, 43, 81, 91 befindet sich zwischen einer ersten und zweiten Elektrode zum Anlegen einer Lesespannung an das Phasenänderungsmaterial, um den programmierten Zellzustand auszulesen. Eine elektrisch leitende Komponente 26, 42, 84, 94 erstreckt sich in einer Richtung zwischen den Elektroden in Kontakt mit dem Phasenänderungsmaterial 21, 43, 81, 91. Die elektrisch leitende Komponente 26, 42, 84, 94 ist so angeordnet, dass sie einem durch die Lesespannung erzeugten Zellstrom einen Strompfad mit einem geringerem Widerstand präsentiert als die amorphe Phase des Phasenänderungsmaterials in einem der Zellzustände, wobei der Strompfad eine Länge aufweist, die von der Größe der amorphen Phase abhängt. Das Volumen der elektrisch leitenden Komponente 26, 42, 84, 94 ist größer als etwa halb so groß wie das des Phasenänderungsmaterials 21, 43, 81, 91. Der Widerstand pro Längeneinheit der elektrisch leitenden Komponente 26, 42, 84, 94 kann in der Richtung des Strompfads variieren, um dadurch eine gewünschtes Zell-Betriebscharakteristik bereitzustellen.
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公开(公告)号：GB2515101A
公开(公告)日：2014-12-17
申请号：GB201310630
申请日：2013-06-14
Applicant: IBM
Inventor： SANGBUM KIM , KREBS DANIEL , LAM HON CHUNG , POZIDIS CHARALAMPOS
Abstract: Phase-change memory cells 40 are provided for storing information in a plurality of programmable cell states. A phase-change material 41 is located between first and second electrodes 42,43 for applying a read voltage to the phase-change material to read the programmed cell state. An electrically-conductive component 44 and comprising for example Tantalum Nitride (TaN) or Titanium Aluminium Nitride (TiAlN) extends from one electrode to the other, but also is in contact with the phase-change material 41. The resistance presented by the electrically conductive component 44 to a cell current produced by the read voltage placed across the electrodes 43,46 is less than that of the amorphous phase, and greater than that of the crystalline phase, of the phase-change material 41 in any of said cell states. The electrically conductive material may form a sheath or lining surrounding the phase change material 41 and may comprise of layers of material ranging between 1 and 5nm. The sheath may have a base portion disposed between the phase change material and the electrode and may be in contact with both electrodes. The phase change material in cross section may be smaller or narrower near one of the electrodes. The cell may store more than two levels or information s>2. The memory device may further comprise an array of phase change memory cells and a read write controller for reading and writing data.
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公开(公告)号：GB2500694A
公开(公告)日：2013-10-02
申请号：GB201205686
申请日：2012-03-30
Applicant: IBM
Inventor： KREBS DANIEL , SEBASTIAN ABU
Abstract: A phase-change memory cell 10 comprising: at least a reference electrical terminal T3; at least two electrical terminals T1, T2 that are configurable to be supplied with respective electrical signals S1, S2 and at least a phase-change material 11such as germanium antimony tellurium alloy that is provided between, and coupled to each of, the reference electrical terminal T3 and the two electrical terminals T1, T2, the phase-change material 11 being operable in one of at least two reversibly transformable phases, an amorphous phase 11' and a crystalline phase 11", a transition from one phase to the other phase occurring in response to a corresponding phase-altering electrical signal being applied to the phase-change material 11, wherein when the phase-change memory cell 10 is in use: the respective electrical signals S1, S2 supplied to the electrical terminals T1, T2 are configurable to comprise a phase-altering signal, at least a resistance measurement unit 13 is accessible to measure a respective electrical resistance R1, R2 between each of the electrical terminals T1, T2 and the reference electrical terminal T3, and at least a mathematical operation unit 14 is accessible to determine at least a mathematical relation between the respective electrical resistances R1, R2 measured between each of the electrical terminals T1, T2 and the reference electrical terminal T3.
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