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公开(公告)号：GB2525397A
公开(公告)日：2015-10-28
申请号：GB201407089
申请日：2014-04-22
Applicant: IBM
Inventor： KREBS DANIEL , GALLO MANUEL LE , SEBASTIAN ABU
Abstract: The invention relates a device and method for determining an actual level (L) of a multi level resistive memory cell having a plurality of programmable levels. The device comprises an estimator unit 110 and a detection unit 120 . The estimator unit 110 is adapted to receive a time input signal, t and a temperature input signal T and to estimate changes of a read-out signal of the levels of the resistive memory cell based on a time and temperature dependent model of the resistance changes, the received time input signal t and the received temperature input signal T. The detection unit is adapted to receive an actual read-out signal from the resistive memory cell and the estimated changes from the estimator unit. Further, the detection unit is adapted to determine the actual level of the resistive memory cell based on the received read-out signal and the received estimated changes. The estimator unit may be based on a model of a combination of a structural relaxation model and an electrical transport model. The structural relaxation model may be based on transitions between neighbouring states of the resistive memory corresponding to local minima.
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公开(公告)号：GB2515567A
公开(公告)日：2014-12-31
申请号：GB201311670
申请日：2013-06-28
Applicant: IBM
Inventor： KREBS DANIEL , SEBASTIAN ABU
Abstract: Phase-change memory cells 20 for storing information in plural programmable cell states comprise a phase-change component 21 comprising opposed layers 24a, 24b of phase-change material extending between two electrodes 22, 23 for applying a read voltage to the phase-change component. A core component 25 which may be a nanowire is in contact with respective inner surfaces of the layers of phase-change material, which may join to form an annulus around the core component (Fig. 4b), and which may be closed at one end by a base layer 28. An outer component 26 is in contact with respective outer surfaces of the opposed layers of phase-change material. At least one of the core component and the outer component is formed of electrically-conductive material and presents a lower-resistance current path to the cell current produced by the read voltage than the amorphous phase of the phase-change material in any of the cell states, the current path having a length dependent on size of the amorphous phase in the opposed layers (Fig. 5). Intermediate cell states can occur when the phase change component comprises both amorphous regions 30 and crystalline regions 31 in varying proportions. The outer component thickness may vary in a direction between the electrodes (Fig. 15) to modify the programming curve, or it may be formed of alternate lower and higher resistance conductive sections (Fig. 16; 92, 93, 94) giving a stepped operating curve (Fig. 17).
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公开(公告)号：GB2486618B
公开(公告)日：2014-05-14
申请号：GB201206876
申请日：2010-11-10
Applicant: IBM
Inventor： BREITWISCH MATTHEW J , LAM CHUNG HON , RAJENDRAN BIPIN , RAOUX SIMONE , SCHROTT ALEJANDRO G , KREBS DANIEL
Abstract: A phase change memory cell that includes a bottom electrode, a top electrode separated from the bottom electrode, and growth-dominated phase change material deposited between the bottom electrode and the top electrode and contacting the bottom electrode and the top electrode and surrounded by insulation material at sidewalls thereof. The phase change memory cell in a reset state only includes an amorphous phase of the growth-dominated phase change material within an active volume of the phase change memory cell.
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公开(公告)号：GB2515100A
公开(公告)日：2014-12-17
申请号：GB201310629
申请日：2013-06-14
Applicant: IBM
Inventor： KREBS DANIEL , SEBASTIAN ABU
Abstract: Phase-change memory cells 20 are provided for storing information in a plurality of programmable cell states. A phase-change material 21 is located between first 22 and second 23 electrodes for applying a read voltage (see figure 6) to the phase-change material to read the programmed cell state. An electrically-conductive component 26 extends in a direction between the electrodes in contact with the phase-change material 21. The electrically-conductive component 26 is arranged to present, to a cell current produced by the read voltage, a lower-resistance current path than the amorphous phase of the phase-change material in any of the cell states, the current path having a length dependent on the size or quantity of the amorphous phase. The volume of the electrically-conductive component 26 is greater than about half that of said phase-change material 21. The resistance per unit length of the electrically-conductive component 26 may vary in the direction of said current path, such as to provide a desired cell operating characteristic. In one embodiment the phase change material 21 is surrounded by the electrically conductive material 26 forming a cylindrical or concentric structure (figures 3 and 4). The electrically conductive material may be wider near one of the electrodes, or the phase change material maybe wider near one of the electrodes than the other electrode (figures 14, 15). The electrically conductive component may comprise of tantalum nitride TaN and in one embodiment form a sheath or cylinder around the phase change material. Other embodiments are shown in figures 17-19, which have a linear, planar or cylindrical structure on a planar substrate and whereby the electrically conductive material is present on one side of the phase change material only, and does not surround the phase change material.
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公开(公告)号：DE102013216219A1
公开(公告)日：2014-03-06
申请号：DE102013216219
申请日：2013-08-15
Applicant: IBM
Inventor： KREBS DANIEL , SEBASTIAN ABU
Abstract: Die vorliegende Erfindung betrifft einen Halbleiterstapel (1) für die Durchführung mindestens einer logischen Operation, aufweisend: benachbarte Schichten (2, 2'), die in einer gestapelten Konfiguration angeordnet sind, wobei jede Schicht (2, 2') mindestens eine Phasenwechsel-Speicherzelle aufweist, in welcher ein Phasenwechselmaterial (3) zwischen einem elektrischen Heizanschluss (T2, T9) und mindestens zwei weiteren elektrischen Heizanschlüssen (T5, T6) bereitgestellt ist, wobei das Phasenwechselmaterial (3) zwischen dem elektrischen Heizanschluss (T2, T9) und jedem der zwei weiteren elektrischen Heizanschlüsse (T5, T6) in einer von mindestens zwei reversibel umwandelbaren Phasen, einer amorphen Phase (3') und einer kristallinen Phase (3''), zu betreiben ist, wobei der Halbleiterstapel, wenn er in Verwendung ist, dafür konfigurierbar ist, dass er Informationen mittels eines elektrischen Widerstands (R2, R8, R3, R9) der Phase (3'', 3') des Phasenwechselmaterials (3) zwischen jedem elektrischen Heizanschluss (T2, T9) und jedem der zwei weiteren elektrischen Heizanschlüsse (T5, T6) in jeder Schicht (2, 2') speichert, und die logische Operation auf der Grundlage der in den benachbarten Schichten (2, 2') gespeicherten Informationen durchgeführt wird.
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Patent Agency Ranking
公开(公告)号：DE112010004406B4
公开(公告)日：2021-11-18
申请号：DE112010004406
申请日：2010-11-10
Applicant: IBM
Inventor： BREITWISCH MATTHEW J , LAM CHUNG H , RAJENDRAN BIPIN , RAOUX SIMONE , SCHROTT ALEJANDRO G , KREBS DANIEL
IPC: H01L27/24
Abstract: Phasenwechsel-Speicherzelle, umfassend:- eine untere Elektrode (202),- eine obere Elektrode (206), getrennt von der unteren Elektrode, und- wachstumsdominiertes Phasenwechsel-Material (205), in einer Säule (204) zwischen der unteren Elektrode und der oberen Elektrode und die untere Elektrode und die obere Elektrode kontaktierend und seitlich von Isoliermaterial (208) umgeben,- wobei die Phasenwechsel-Speicherzelle in einem Reset- Zustand nur eine amorphe Phase des wachstumsdominierten Phasenwechsel-Materials (205) in der Säule (204) umfasst,- sich in der Phasenwechsel-Speicherzelle zwischen Gallium-Atome umfassenden Grenzflächenbereichen (207a, 207b) des wachstumsdominierten Phasenwechsel-Materials an der unteren Elektrode (202) und an der oberen Elektrode (206) ein Strompfad ausbildet und- das Phasenwechsel-Material (205) nach dem Reset-Vorgang vollständig amorph ist, wenn ein Reset-Strom mit einem vorgegebenen Wert entlang des Strompfads fließt.
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公开(公告)号：GB2505429A
公开(公告)日：2014-03-05
申请号：GB201215340
申请日：2012-08-29
Applicant: IBM
Inventor： KREBS DANIEL , SEBASTIAN ABU
Abstract: The present invention relates to a semiconductor slack 1 for performing at least a logic operation comprising: adjacent layers 2, 2' arranged in a stacked configuration with each layer 2, 2' comprising at least a phase-change memory (PCM) cell in which a phase-change material 3 is provided between a heater electrical terminal T2, T9 and at least two further heater electrical terminals T5, T6, the phase-change material 3 between the heater electrical terminal T2, T9 and each of the two further heater electrical terminals T5, T6 being operable in one of at least two reversibly transformable phases, an amorphous phase 3' and a crystalline phase 3", wherein the semiconductor stack, when in use, is configurable to store information by way of an electrical resistance R2, R8, R3, R9 of the phase 3", 3' of the phase-change material 3 between each heater electrical terminal T2, T9 and each of the two further heater electrical terminals T5, T6 in each layer 2, 2', and the logic operation is performed on the basis of the information stored in the adjacent layers 2, 2'. Depending on the read process pursued the logic operation may comprise a logic AND or a logic OR function. A method of operation of the semiconductor stack is also disclosed. There is further disclosure (figure 2) of a multi-terminal embodiment having for example seven heater electrical terminals allowing for complex logic operation on the multi-terminals. Further embodiments may include more than two stacked phase change memory cells in both two (2D) and three (3D) dimensions.
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公开(公告)号：GB2502568A
公开(公告)日：2013-12-04
申请号：GB201209652
申请日：2012-05-31
Applicant: IBM
Inventor： KREBS DANIEL , CLOSE GAEL
Abstract: Memory apparatus 12 includes a plurality of gated phase-change memory cells 15 having two or more programmable cell-states, the cells 15 each having a gate Gn and being arranged in series between a source and drain. The apparatus further includes a bias voltage generator 21, for applying a bias voltage to the gate of each cell 15, and a controller 22. The controller 22 is adapted to control the bias voltage generator 21, in a write operation for programming the state of a cell 15, to apply a first bias voltage to the gate of each cell except an addressed cell for the write operation. Application of the first bias voltage to a cell 15 reduces the cell resistance such that application of a programming signal (via R/W signal generator 20) between said source and drain affects programming of the addressed cell only. The same bias voltage control mechanism can be used to address cells for read operations.
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公开(公告)号：DE112010004406T5
公开(公告)日：2012-12-13
申请号：DE112010004406
申请日：2010-11-10
Applicant: IBM
Inventor： LAM CHUNG H , RAJENDRAN BIPIN , RAOUX SIMONE , KREBS DANIEL , BREITWISCH MATTHEW J , SCHROTT ALEJANDRO G
IPC: H01L27/24
Abstract: Phasenwechsel-Speicherzelle, umfassend eine untere Elektrode, eine obere Elektrode, getrennt von der unteren Elektrode, und wachstumsdominiertes Phasenwechsel-Material abgeschieden zwischen der unteren Elektrode und der oberen Elektrode und kontaktierend die untere Elektrode und die obere Elektrode und umgeben von Isoliermaterial an den Seitenwänden davon. Die Phasenwechsel-Speicherzelle in einem Reset-Zustand umfasst nur eine amorphe Phase des wachstumsdominierten Phasenwechsel-Materials in einem aktiven Volumen der Phasenwechsel-Speicherzelle.
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公开(公告)号：GB2517696A
公开(公告)日：2015-03-04
申请号：GB201315193
申请日：2013-08-27
Applicant: IBM
Inventor： RAINO GABRIELE , KREBS DANIEL
Abstract: A plurality of nano devices 2 arranged with nanoscale spacing and a thermal deflector 10 located between at least one pair of the nano devices 2. The deflector 10 or thermal heat sink is adapted to deflect thermal near-field radiation emanating from one nano device of the pair away from the other nano device of the pair. The deflector may comprise at least one nanoelement 11 arranged 10 to deflect the thermal near-field radiation. The nanoelement may comprise a discrete region of material, for example a quantum dot 11 having a plasmon-polariton frequency tuned in dependence on the thermal near-field radiation to be deflected. The discrete region may comprise a two dimensional electron gas, whilst the material may comprise a doped semiconductor for example including silicon. The deflector may comprise at least one chain of nano elements arranged to transport thermal energy due to the thermal near-field radiation along the chain. The nano element resonant frequency may vary along the chain. The nano device may comprise a phase change memory cell arranged in an array and in particular adapted to deflect thermal near field radiation during a RESET operation. The nano device may comprise TiN electrodes 4,5 and SiN insulating walls surrounding the phase change material (PCM) 3 which may be a chalcogenide.
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