公开(公告)号：WO2005024900A3

公开(公告)日：2005-06-09

申请号：PCT/US2004021345

申请日：2004-07-01

Applicant: IBM ,  KHATER MARWAN H ,  DUNN JAMES S ,  HARAME DAVID L ,  JOSEPH ALVIN J ,  LIU QIZHI ,  PAGETTE FRANCOIS ,  ST ONGE STEPHEN A ,  STRICKER ANDREAS D

Inventor： KHATER MARWAN H ,  DUNN JAMES S ,  HARAME DAVID L ,  JOSEPH ALVIN J ,  LIU QIZHI ,  PAGETTE FRANCOIS ,  ST ONGE STEPHEN A ,  STRICKER ANDREAS D

IPC: H01L21/331 ,  H01L29/10 ,  H01L29/732 ,  H01L29/737 ,  H01L23/62

CPC classification number: H01L29/66287 ,  H01L29/1004 ,  H01L29/66242 ,  H01L29/732 ,  H01L29/7378

Abstract: A bipolar transistor with raised extrinsic base and selectable self-alignment between the extrinsic base and the emitter (106) is disclosed. The fabrication method may include the formation of a predefined thickness of a first extrinsic base layer (102) of polysilicon or silicon on an intrinsic base (108). A dielectric landing pad (128) is then formed by lithography on the first extrinsic base layer (102). Next, a second extrinsic base layer (104) of polysilicon or silicon is formed on top of the dielectric landing pad (128) to finalize the raised extrinsic base total thickness. An emitter (106) opening is formed using lithography and RIE, where the second extrinsic base layer (104) is etched stopping on the dielectric landing pad (128). The degree of self-alignment between the emitter (106) and the raised extrinsic base is achieved by selecting the first extrinsic base layer (102) thickness, the dielectric landing pad (128) width, and the spacer width.

Abstract translation: 公开了一种具有凸起的非本征基极和在本征基极和发射极（106）之间的可选自对准的双极晶体管。 制造方法可以包括在内在基极（108）上形成多晶硅或硅的第一非本征基极层（102）的预定厚度。 然后通过光刻在第一非本征基极层（102）上形成电介质着色焊盘（128）。 接下来，在电介质着色焊盘（128）的顶部上形成多晶硅或硅的第二非本征基极层（104），以最终确定凸出的非本征基本总厚度。 使用光刻和RIE形成发射器（106）开口，其中第二外部基极层（104）被蚀刻停止在电介质着色焊盘（128）上。 通过选择第一非本征基极层（102）的厚度，电介质着陆焊盘（128）的宽度和间隔物宽度来实现发射极（106）和凸起的外在基极之间的自对准程度。

公开(公告)号：WO2005004201A3

公开(公告)日：2005-05-12

申请号：PCT/US2004019906

申请日：2004-06-22

Applicant: IBM ,  JOSEPH ALVIN J ,  LIU QIZHI

Inventor： JOSEPH ALVIN J ,  LIU QIZHI

IPC: H01L21/331 ,  H01L21/8249 ,  H01L27/06 ,  H01L29/10 ,  H01L29/732 ,  H01L21/8222 ,  H01L27/082

CPC classification number: H01L29/66287 ,  H01L21/8249 ,  H01L27/0623 ,  H01L29/1004 ,  H01L29/732

Abstract: A high fT and fmax bipolar transistor (100) includes an emitter (104), a base (120), and a collector (116). The emitter has a lower portion (108) and an upper portion (1.12) that extends beyond the lower portion. The base includes an intrinsic base (140) and an extrinsic base (144). The intrinsic base is located between the lower portion of the emitter and the collector. The extrinsic base extends from the lower portion of the emitter beyond the upper portion of the emitter and includes a continuous conductor (148) that extends from underneath the upper portion of the emitter and out from underneath the upper portion of the emitter. The continuous conductor provides a low electrical resistance path from a base contact (not shown) to the intrinsic base. The transistor may include a second conductor (152) that does not extend underneath the upper portion of the emitter, but which further reduces the electrical resistance through the extrinsic base.

Abstract translation: 高fT和fmax双极晶体管（100）包括发射极（104），基极（120）和集电极（116）。 发射器具有延伸超出下部的下部（108）和上部（1.12）。 基底包括本征基（140）和外基（144）。 本征基极位于发射极的下部和集电极之间。 外部基极从发射器的下部延伸超过发射器的上部，并且包括从发射器的上部下方延伸并从发射器的上部下方延伸的连续导体（148）。 连续导体提供从底部触点（未示出）到本征基极的低电阻路径。 晶体管可以包括第二导体（152），其不延伸在发射极的上部下方，但是通过外部基极进一步减小电阻。

公开(公告)号：GB2506816A

公开(公告)日：2014-04-09

申请号：GB201401778

申请日：2012-06-21

Applicant: IBM

Inventor： CAMILLO-CASTILLO RENATA ,  GRAY PETER B ,  HARAME DAVID L ,  JOSEPH ALVIN ,  KHATER MARWAN ,  LIU QIZHI

IPC: H01L21/8249 ,  H01L29/732

Abstract: Methods for fabricating bipolar junction transistors, bipolar junction transistors made by the methods, and design structures for a bipolar junction transistor. The bipolar junction transistor (80) includes a dielectric layer (32) on an intrinsic base (84) and an extrinsic base (82) at least partially separated from the intrinsic base by the dielectric layer. An emitter opening (52) extends through the extrinsic base and the dielectric layer. The dielectric layer is recessed laterally relative to the emitter opening to define a cavity (60a, 60b) between the intrinsic base and the extrinsic base. The cavity is filled with a semiconductor layer (64) that physically links the extrinsic base and the intrinsic base together.

公开(公告)号：DE112012002434T5

公开(公告)日：2014-03-06

申请号：DE112012002434

申请日：2012-06-21

Applicant: IBM

Inventor： CAMILLO-CASTILLO RENATA ,  HARAME DAVID L ,  JOSEPH ALVIN J ,  LIU QIZHI ,  GRAY PETER B ,  KHATER MARWAN H

IPC: H01L29/73

Abstract: Verfahren zum Herstellen von Bipolartransistoren, Bipolartransistoren, die mittels der Verfahren hergestellt werden, sowie Entwurfsstrukturen für einen Bipolartransistor. Der Bipolartransistor (80) beinhaltet eine dielektrische Schicht (32) auf einer intrinsischen Basis (84) und eine extrinsische Basis (82), die durch die dielektrische Schicht wenigstens teilweise von der intrinsischen Basis getrennt ist. Eine Emitter-Öffnung (52) erstreckt sich durch die extrinsische Basis und die dielektrische Schicht hindurch. Die dielektrische Schicht ist lateral relativ zu der Emitter-Öffnung vertieft, um einen Hohlraum (60a, 60b) zwischen der intrinsischen Basis und der extrinsischen Basis zu definieren. Der Hohlraum ist mit einer Halbleiterschicht (64) gefüllt, welche die extrinsische Basis und die intrinsische Basis physisch miteinander verbindet.

公开(公告)号：GB2497177A

公开(公告)日：2013-06-05

申请号：GB201220384

申请日：2012-11-13

Applicant: IBM

Inventor： HARAME DAVID L ,  LIU QIZHI ,  PEKARIK JOHN JOSEPH ,  ELLIS-MONAGHAN JOHN JOSEPH ,  ADKISSON JAMES WILLIAM

IPC: H01L29/08 ,  H01L29/737

Abstract: A heterojunction bipolar transistor 100 and a method of forming the heterojunction bipolar transistor with a raised collector pedestal 125 in reduced dimension for reduced base-collector junction capacitance. The raised collector pedestal 125 is on the top surface of a substrate 121, 120, 101 and extends vertically through dielectric layer(s) 103, 104. The raised collector pedestal is un-doped or low-doped and is aligned above a sub-collector region 120, 121 contained within the substrate 101 and is narrower than that sub-collector region 120. An intrinsic base layer 105,132/131 is above the raised collector pedestal and the dielectric layer(s) 103, 104. An extrinsic base layer 141 is above the intrinsic base layer 132, 131. Thus, the space between the extrinsic base layer and the sub-collector region is increased. This increased space is filled by dielectric material and the electrical connection between the intrinsic base layer and the sub-collector region is provided by the relatively narrow, un-doped or low-doped, raised collector pedestal. Consequently the base-collector junction capacitance is reduced and the maximum oscillation frequency (fmax) is increased.

公开(公告)号：GB2506816B

公开(公告)日：2015-09-09

申请号：GB201401778

申请日：2012-06-21

Applicant: IBM

Inventor： CAMILLO-CASTILLO RENATA ,  GRAY PETER B ,  HARAME DAVID LOUIS ,  JOSEPH ALVIN J ,  KHATER MARWAN H ,  LIU QIZHI

IPC: H01L21/8249 ,  H01L29/732

Abstract: Methods for fabricating bipolar junction transistors, bipolar junction transistors made by the methods, and design structures for a bipolar junction transistor. The bipolar junction transistor includes a dielectric layer on an intrinsic base and an extrinsic base at least partially separated from the intrinsic base by the dielectric layer. An emitter opening extends through the extrinsic base and the dielectric layer. The dielectric layer is recessed laterally relative to the emitter opening to define a cavity between the intrinsic base and the extrinsic base. The cavity is filled with a semiconductor layer that physically links the extrinsic base and the intrinsic base together.