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    Pixel sensor structure and method for manufacturing semiconductor structure (funnel-shaped optical pipe for pixel sensor)
    1.
    发明专利
    Pixel sensor structure and method for manufacturing semiconductor structure (funnel-shaped optical pipe for pixel sensor) 审中-公开
    像素传感器结构和制造半导体结构的方法（用于像素传感器的FUNNEL形状光学管道）

    公开(公告)号：JP2008141014A

    公开(公告)日：2008-06-19

    申请号：JP2006326348

    申请日：2006-12-01

    Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

    Inventor： RASSEL RICHARD JOHN ,  GAMBINO JEFFREY PETER ,  ADKISSON JAMES WILLIAM ,  LEIDY ROBERT KENNETH

    IPC: H01L27/14

    Abstract: PROBLEM TO BE SOLVED: To provide an optical sensor structure and a method for forming the structure.
    SOLUTION: The optical sensor structure contains (a) a semiconductor substrate and (b) a light-collecting region on the semiconductor substrate. Also, the optical sensor structure contains a funnel-shaped optical pipe on the light-collecting region. The funnel-shaped optical pipe contains (i) a lower cylindrical portion on the light-collecting region and (ii) a funnel-shaped portion, having a tapering shape and arranged on the lower cylindrical portion, while physically coming into direct contact with the lower cylindrical portion. This structure further contains a color filter region on the funnel-shaped optical pipe.
    COPYRIGHT: (C)2008,JPO&INPIT

    Abstract translation: 要解决的问题：提供一种光学传感器结构和形成该结构的方法。 解决方案：光学传感器结构包含（a）半导体衬底和（b）半导体衬底上的聚光区域。 此外，光学传感器结构在光收集区域上包含漏斗形光管。 漏斗状光学管道包括（i）集光区域上的下圆筒部分和（ii）锥形部分，其具有锥形形状并且布置在下圆柱形部分上，同时物理上直接接触 下圆柱形部分。 该结构还在漏斗状的光导管上含有滤色器区域。 版权所有（C）2008，JPO＆INPIT

    Pixel sensor cell and method of manufacturing the same (photodiode of cmos imaging device having increased capacitance)
    2.
    发明专利
    Pixel sensor cell and method of manufacturing the same (photodiode of cmos imaging device having increased capacitance) 有权
    像素传感器单元及其制造方法（具有增加电容的CMOS成像装置的光电二极管）

    公开(公告)号：JP2007221121A

    公开(公告)日：2007-08-30

    申请号：JP2007025034

    申请日：2007-02-05

    Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

    Inventor： ELLIS-MONAGHAN JOHN JOSEPH ,  PEARSON DALE JONATHAN ,  ADKISSON JAMES WILLIAM ,  DENNIS L ROGERS ,  MARK D JAFFE

    IPC: H01L27/146 ,  H01L31/10

    CPC classification number: H01L27/14643 ,  H01L27/1463 ,  H01L27/14689 ,  H01L31/035281

    Abstract: PROBLEM TO BE SOLVED: To provide a CMOS image sensor having a photodetector diode formed on the side wall of a deep trench, achieving separation of a collector, and thus simplifying a process.
    SOLUTION: A pixel sensor cell includes a semiconductor substrate having a surface, and a photoelectric element having a non-transversely oriented charge collection area which is formed on the substrate and is completely separated from a physical boundary including the substrate surface. The photoelectric element includes a trench which is formed on the substrate made of a first conductive material and has side walls, a first doped layer which is formed beside at least one of the side walls and is made of a second conductive material, and a second doped layer which is formed between the first doped layer and at least one of the trench side walls and is further formed on the substrate surface. The second doped layer separates the first doped layer from at least one of the trench side walls and the substrate surface.
    COPYRIGHT: (C)2007,JPO&INPIT

    Abstract translation: 要解决的问题：为了提供一种具有形成在深沟槽的侧壁上的光电检测器二极管的CMOS图像传感器，实现了集电极的分离，从而简化了工艺。 解决方案：像素传感器单元包括具有表面的半导体基板和具有非横向取向的电荷收集区的光电元件，其形成在基板上并与包括基板表面的物理边界完全分离。 光电元件包括​​形成在由第一导电材料制成并具有侧壁的基板上的沟槽，第一掺杂层，其形成在至少一个侧壁旁边并由第二导电材料制成，第二掺杂层 掺杂层，其形成在第一掺杂层和至少一个沟槽侧壁之间，并进一步形成在衬底表面上。 第二掺杂层将第一掺杂层与沟槽侧壁和衬底表面中的至少一个分开。 版权所有（C）2007，JPO＆INPIT

    Image sensor and method of manufacturing the same
    3.
    发明专利
    Image sensor and method of manufacturing the same 有权
    图像传感器及其制造方法

    公开(公告)号：JP2011054963A

    公开(公告)日：2011-03-17

    申请号：JP2010186851

    申请日：2010-08-24

    Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

    Inventor： GAMBINO JEFFREY P ,  ELLIS-MONAGHAN JOHN JOSEPH ,  ADKISSON JAMES WILLIAM ,  LEIDY ROBERT KENNETH

    IPC: H01L27/14 ,  H01L27/146

    CPC classification number: H01L27/14643 ,  H01L27/14621 ,  H01L27/14625 ,  H01L27/1464 ,  H01L27/14683 ,  H01L27/14685

    Abstract: PROBLEM TO BE SOLVED: To provide a solid-state image sensor and a method of manufacturing the same. SOLUTION: A solid-state image sensor has a substrate on which a photosensitive region is provided. In the solid-state image sensor, an nonuniform reflection layer is arranged, on a side opposite to the incidence side of the emitted light of the photosensitive region. The nonuniform reflecting layer has a shape for reflecting an incident emitted light that is not captured by one photosensitive region at first to return it to the photosensitive area, whereas which does not reflect the incident emitted light that is not captured by the one photosensitive region, at first, to other photosensitive region provided adjacent to the one photosensitive region on the substrate. COPYRIGHT: (C)2011,JPO&INPIT

    Abstract translation: 要解决的问题：提供一种固态图像传感器及其制造方法。 解决方案：固态图像传感器具有设置有感光区域的基板。 在固态图像传感器中，在与感光区域的发射光的入射侧相反的一侧上布置不均匀的反射层。 不均匀反射层具有用于反射未被一个感光区域捕获的入射发射光首先返回到感光区域的形状，而不反射未被一个感光区域捕获的入射发射光， 首先是与衬底上的一个感光区域相邻设置的其它感光区域。 版权所有（C）2011，JPO＆INPIT

    Asymmetric anti-halo field effect transistor
    5.
    发明专利
    Asymmetric anti-halo field effect transistor 未知

    公开(公告)号：GB2498621A

    公开(公告)日：2013-07-24

    申请号：GB201221477

    申请日：2012-11-29

    Applicant: IBM

    Inventor： BRYANT ANDRES ,  NOWAK EDWARD ,  ANDERSON BRENT ALAN ,  ADKISSON JAMES WILLIAM

    IPC: H01L29/66 ,  H01L21/265 ,  H01L21/266 ,  H01L21/8232 ,  H01L21/8234 ,  H01L21/8238 ,  H01L29/10 ,  H01L29/423

    Abstract: In a method of forming an integrated circuit structure, a first compensating implant (Fig. 2; 120) with opposite dopant polarity to the semiconductor channel implant (Fig. 1; 114) is implanted uniformly into a substrate for example a silicon on insulator (SOI) substrate, to a depth shallower than a semiconductor channel implant depth. A mask 130 is patterned on the first compensating implant 122 in the substrate, including an opening 138 exposing a channel location of the substrate. A second compensating implant 140 called an anti-halo implant has doping polarity the same as the channel implant polarity, and is implanted into the channel location through the mask opening in the channel location and at an angle offset from perpendicular to the top surface of the substrate. The second compensating implant 142 is particularly useful for long channel transistors. It is positioned closer to a first side of the channel location relative to an opposite second side of the channel location. A gate insulator layer 132 and gate conductor (Fig. 5; 152) are formed above the channel location of the substrate in the mask opening 138. The mask is removed to leave the gate conductor standing on the channel location of the substrate. Source and drain extension regions (Fig. 6; 162) are formed by implanting using the gate structure as a mask, after which gate sidewalls (Fig. 7; 170) are formed and source and drain implants (Fig. 7; 174, 176) are implanted using the gate sidewalls as masks. The width of the anti-halo implant 142 is automatically matched to the width of gate.

    Switchable piezoelectric filters using micro-electro-mechanical beam and design structures
    6.
    发明专利
    Switchable piezoelectric filters using micro-electro-mechanical beam and design structures 未知

    公开(公告)号：GB2498261A

    公开(公告)日：2013-07-10

    申请号：GB201223287

    申请日：2012-12-21

    Applicant: IBM

    Inventor： JAFFE MARK DAVID ,  ADKISSON JAMES WILLIAM ,  STAMPER ANTHONY K ,  WOLF RANDY LEE ,  CANDRA PANGLIJEN ,  GAMBINO JEFFERY P ,  DUNBAR THOMAS J

    IPC: H01L41/047 ,  H01L41/107 ,  H03H9/02 ,  H03H9/64

    Abstract: Switchable and/or tunable filters, methods of manufacture and design structures are disclosed herein. The method of forming the filters includes forming at least one piezoelectric (PE) filter structure comprising a plurality of electrodes 14, 16 formed on a PE 12. The method further includes forming a micro-electro-mechanical structure (MEMS) comprising a MEMS beam 26 formed above the PE substrate and at a location in which, upon actuation, the MEMS beam shorts the PE filter structure by contacting at least one of the plurality of electrodes. The PE filter may be surface acoustic wave (SAW) filter. The SAW filter may comprise input and output transducers comprising interleaved electrodes. The PE filter may be a bulk acoustic wave (BAW) filter. The beam may be perpendicular to the interleaved electrodes and may cover the whole area of the electrodes of at least one filter structure. The structure may be formed using computer aided design. In one embodiment the frequency of a filter may be determined and the beam may be actuated to contact one of the electrodes depending on the frequency.

    Bipolar transistor comprising a raised collector pedestal for reduced capacitance
    8.
    发明专利
    Bipolar transistor comprising a raised collector pedestal for reduced capacitance 未知

    公开(公告)号：GB2497177A

    公开(公告)日：2013-06-05

    申请号：GB201220384

    申请日：2012-11-13

    Applicant: IBM

    Inventor： HARAME DAVID L ,  LIU QIZHI ,  PEKARIK JOHN JOSEPH ,  ELLIS-MONAGHAN JOHN JOSEPH ,  ADKISSON JAMES WILLIAM

    IPC: H01L29/08 ,  H01L29/737

    Abstract: A heterojunction bipolar transistor 100 and a method of forming the heterojunction bipolar transistor with a raised collector pedestal 125 in reduced dimension for reduced base-collector junction capacitance. The raised collector pedestal 125 is on the top surface of a substrate 121, 120, 101 and extends vertically through dielectric layer(s) 103, 104. The raised collector pedestal is un-doped or low-doped and is aligned above a sub-collector region 120, 121 contained within the substrate 101 and is narrower than that sub-collector region 120. An intrinsic base layer 105,132/131 is above the raised collector pedestal and the dielectric layer(s) 103, 104. An extrinsic base layer 141 is above the intrinsic base layer 132, 131. Thus, the space between the extrinsic base layer and the sub-collector region is increased. This increased space is filled by dielectric material and the electrical connection between the intrinsic base layer and the sub-collector region is provided by the relatively narrow, un-doped or low-doped, raised collector pedestal. Consequently the base-collector junction capacitance is reduced and the maximum oscillation frequency (fmax) is increased.

    Asymmetric anti-halo field effect transistor
    10.
    发明专利
    Asymmetric anti-halo field effect transistor 未知

    公开(公告)号：GB2498621B

    公开(公告)日：2014-01-01

    申请号：GB201221477

    申请日：2012-11-29

    Applicant: IBM

    Inventor： BRYANT ANDRES ,  NOWAK EDWARD ,  ANDERSON BRENT ALAN ,  ADKISSON JAMES WILLIAM

    IPC: H01L29/66 ,  H01L21/265 ,  H01L21/266 ,  H01L21/8232 ,  H01L21/8234 ,  H01L21/8238 ,  H01L29/10 ,  H01L29/423

    Abstract: A method of forming an integrated circuit structure implants a first compensating implant into a substrate. The method patterns a mask on the first compensating implant in the substrate. The mask includes an opening exposing a channel location of the substrate. The method implants a second compensating implant into the channel location of the substrate. The second compensating implant is made through the opening in the mask and at an angle that is offset from perpendicular to the top surface of the substrate. The second compensating implant is positioned closer to a first side of the channel location relative to an opposite second side of the channel location and the second compensating implant comprises a material having the same doping polarity as the semiconductor channel implant. Then, the method forms a gate conductor above the channel location of the substrate in the opening of the mask.

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