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    INTEGRATED SEMICONDUCTOR STRUCTURE AND FABRICATION METHOD
    11.
    发明专利
    INTEGRATED SEMICONDUCTOR STRUCTURE AND FABRICATION METHOD 未知

    公开(公告)号：DE3666753D1

    公开(公告)日：1989-12-07

    申请号：DE3666753

    申请日：1986-05-23

    Applicant: IBM

    Inventor： MALAVIYA SHASHI DHAR

    IPC: H01L29/808 ,  H01L21/033 ,  H01L21/308 ,  H01L21/331 ,  H01L21/337 ,  H01L21/764 ,  H01L21/822 ,  H01L27/04 ,  H01L29/06 ,  H01L29/47 ,  H01L29/73 ,  H01L29/78 ,  H01L29/80 ,  H01L29/86 ,  H01L29/872 ,  H01L29/72 ,  H01L29/36 ,  H01L29/76

    Abstract: Disclosed is a submicron-wide single-crystal silicon structure protruding form a monolithic silicon body (32). This three-dimensional structure includes a lower section (68) of a first (N) conductivity type and an upper section (50) of a second (P) conductivity type. The upper section (50), consisting of narrow top and bottom portions (70, 72) separated by a relatively wide middle portion (56), consitutes the silicon material from which various active or passive integrated circuit devices may be fabricated. For example, in the case of an NPN transistor, the central region of the middle portion (56) constitutes the base region, the emitter and collector being enbed- ded in the two outer side regions thereof in a mutually facing relationship. Electrical contacts to the elements of the structure are established on the top and/or Isides of the protrusion. Owing to its freestanding self-isolated characteristic, dielectric isolation of the device is not necessary. Alternatively, total dielectric isolation of the IC may be achieved by utilizing a dielectric material for the bottom of the protrusion.Disclosed also is a process of fabricating the above structure. In one embodiment, starting with a single crystal N silicon body (32) having a P region, an insulator stud (48) of submicron width and length dictated by the limits of lithography is formed on the P region. Using the stud (48) as a mask, the P 'region is etched forming a narrow top portion (70) having the stud width projecting from the silicon body (32). On the exposed sides of the top portion - (70) oxide walls (52, 54) are formed and the etching continued forming the middle portion (56) of a width exceeding that of the top portion (70). An oxide-nitride wall (58, 60) is established on the exposed sides of the middle portion (56) and, using the resulting structure as a mask, the etching is continued to completely etch through the P region and a substantial portion of the underlying N silicon body - (32) thereby forming a free-standing silicon protrusion structure. By thermal oxidation, thick oxide walls (64, 66) are then formed on the just exposed sides of the silicon. Alternatively, the exposed sides of silicon may be completely oxidized to obtain a fully dielectrically isolated silicon protruding structure.

    3-WAY EXCLUSIVE OR LOGIC CIRCUIT
    13.
    发明专利
    3-WAY EXCLUSIVE OR LOGIC CIRCUIT 未知

    公开(公告)号：DE3070870D1

    公开(公告)日：1985-08-14

    申请号：DE3070870

    申请日：1980-12-12

    Applicant: IBM

    Inventor： MALAVIYA SHASHI DHAR

    IPC: H03K19/013 ,  H03K19/21

    Abstract: A 3-way EXCLUSIVE OR function is performed with an essentially single stage logic delay. A 3-way OR circuit (10) produces a logical "1" output whenever at least one of three input operands is "1". A TWO AND ONLY TWO logic circuit (20A) comprising three 3-way NAND-circuits (22, 24, 26) produces a logical "0" output when two and only two of the three input operands are "1". The outputs of the OR circuit (10) and the TWO AND ONLY TWO logic circuit (20A) are DOT-ANDed at a DOT-AND circuit (30A) to provide the desired EXCLUSIVE OR function.

    15.
    发明专利
    未知

    公开(公告)号：DE69208415T2

    公开(公告)日：1996-09-19

    申请号：DE69208415

    申请日：1992-09-11

    Applicant: IBM

    Inventor： BHATIA HARSARAN SINGH ,  INTERRANTE MARIO JOHN ,  KADAKIA SURESH DAMONDARDAS ,  STOLLER HERBERT IVAN ,  MALAVIYA SHASHI DHAR ,  MCLEOD MARK HARRISON ,  RAY SUDIPTA KUMAR

    IPC: H01L23/12 ,  H01L21/48 ,  H01L23/538 ,  H05K3/00 ,  H05K3/32 ,  H05K3/40

    Abstract: A direct distribution wiring system is provided which facilitates the effecting of repair or engineering change in a Multi-chip module (MCM) while eliminating the need for redistribution and/or buried connections between IC attachment pads and engineering change pads, thus eliminating the need for patterned conductor layers corresponding to such functions. The operation of the MCM is improved by the wiring system allowing the reduction of lumped capacitances by disconnection of defective conductors, accomplished by providing severable connectors in a direct distribution structure, as well as the elimination of redistribution wiring layers and increased IC density on the MCM. Full potential fault coverage as well as full discretion in reversible engineering changes is provided by forming all elements of the wiring system on the surface of the device.

    17.
    发明专利
    未知

    公开(公告)号：DE3484846D1

    公开(公告)日：1991-08-29

    申请号：DE3484846

    申请日：1984-11-14

    Applicant: IBM

    Inventor： JAMBOTKAR CHAKRAPANI GAJANAN ,  MALAVIYA SHASHI DHAR

    IPC: H01L21/033 ,  H01L21/331 ,  H01L21/74 ,  H01L21/76 ,  H01L21/761 ,  H01L21/762 ,  H01L21/822 ,  H01L21/8222 ,  H01L27/04 ,  H01L27/06 ,  H01L29/73 ,  H01L29/732 ,  H01L21/30

    Abstract: A one mask technique for making substrate contact from the top surface of an integrated circuit device. A thin ion implanted region (4) of one conductivity type is formed over the entirety of a major surface of the semiconductor substrate (2). By lithography and etching, a shallow etched region is formed to a depth below the region (4) of the first conductivity type at the substrate surface in an area designated for substitute contacting. A region (12) of a second conductivity type is then formed at the central portion of the etched region. The substrate (2) is then heated to form a buried collector region (14) of the first conductivity type and a portion (12) of the reach-through region of the second conductivity type in the substrate. An epitaxial layer (14) is next formed on the major surface of the substrate. A portion (16) of the substrate reach-through, which is directly above the portion (12) of the substrate reach-through previously formed, is simultaneously formed along with a base region of the second conductivity type for the integrated circuit. Then, emitter and coltector reach-through regions are formed in the epitaxial layer followed by the step of providing electrical contacts. Deep dielectric isolation walls (18) are formed at a suitable stage in the processing.

    20.
    发明专利
    未知

    公开(公告)号：DE2553203A1

    公开(公告)日：1976-07-08

    申请号：DE2553203

    申请日：1975-11-27

    Applicant: IBM

    Inventor： MALAVIYA SHASHI DHAR ,  VORA MADHUKAR B ,  WILSON WILLIAM T

    IPC: H01L27/146 ,  H01L31/112 ,  H04N3/14 ,  H01L27/08

    Abstract: A solid state analog image sensor is disclosed in which the video input to the sensor is stored as a charge on a floating gate in a cell. The cell itself consists of a single J-FET with Schottky barrier contact to the metal word line. All associated address and drive/sense circuits are located around the active cell area. By filling up the active area with only the J-FET's and relegating the rest of the circuitry to the peripheral, inactive region, high picture resolution is obtained.

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