公开(公告)号：GB2321543A

公开(公告)日：1998-07-29

申请号：GB9724340

申请日：1997-11-19

Applicant: IBM

Inventor： MALLICK SOUMMYA ,  MCDONALD ROBERT G ,  SWARTHOUT EDWARD L

IPC: G06F9/48 ,  G06F9/38 ,  G06F9/45

Abstract: A method and system are provided for constructing a program executable by a processor including one or more processing elements for executing threads and a thread scheduler for assigning threads to the processing elements for execution. According to the method, a plurality of threads are provided that each include at least one control flow instruction. From one or more control flow instructions within the plurality of threads, a condition upon which execution of a particular thread depends is determined. In response to the determination, at least one navigation instruction executable by the thread scheduler is created that indicates that the particular thread is to be assigned to one of the processing elements for execution in response to the condition.

公开(公告)号：DE69719235T2

公开(公告)日：2003-10-30

申请号：DE69719235

申请日：1997-04-25

Applicant: IBM

Inventor： MALLICK SOUMMYA ,  LOPER ALBERT JOHN

IPC: G06F9/32 ,  G06F9/38

Abstract: A processor (10) and method for speculatively executing branch instructions utilizing a selected branch prediction methodology are disclosed. The processor has one or more execution units (22, 28, 30) for executing instructions, including a branch processing unit (18) for executing branch instructions. The branch processing unit includes selection logic for selecting one of a plurality of branch prediction methodologies and a branch prediction unit for predicting the resolution of a conditional branch instruction utilizing the selected branch prediction methodology. The branch processing unit further includes execution facilities for speculatively executing the conditional branch instruction based upon the prediction. Based upon the outcome of the prediction, the selection logic selects a branch prediction methodology for predicting a subsequent conditional branch instruction so that branch prediction accuracy is enhanced. In one embodiment, the multiple branch prediction methodologies include static and dynamic branch prediction.

公开(公告)号：AT233414T

公开(公告)日：2003-03-15

申请号：AT97302877

申请日：1997-04-25

Applicant: IBM

Inventor： MALLICK SOUMMYA ,  LOPER ALBERT JOHN

IPC: G06F9/32 ,  G06F9/38

Abstract: A processor (10) and method for speculatively executing branch instructions utilizing a selected branch prediction methodology are disclosed. The processor has one or more execution units (22, 28, 30) for executing instructions, including a branch processing unit (18) for executing branch instructions. The branch processing unit includes selection logic for selecting one of a plurality of branch prediction methodologies and a branch prediction unit for predicting the resolution of a conditional branch instruction utilizing the selected branch prediction methodology. The branch processing unit further includes execution facilities for speculatively executing the conditional branch instruction based upon the prediction. Based upon the outcome of the prediction, the selection logic selects a branch prediction methodology for predicting a subsequent conditional branch instruction so that branch prediction accuracy is enhanced. In one embodiment, the multiple branch prediction methodologies include static and dynamic branch prediction.

公开(公告)号：GB2317976B

公开(公告)日：2001-12-19

申请号：GB9716264

申请日：1997-07-31

Applicant: IBM

Inventor： LOPER ALBERT J ,  MALLICK SOUMMYA

IPC: G06F1/26 ,  G06F1/32 ,  G06F9/38 ,  G06F12/08 ,  G06F15/78 ,  G11C7/00

Abstract: While a set-associative cache memory operates in a first power mode, information is stored in up to N number of ways of the cache memory, where N is an integer number and N>1. While the cache memory operates in a second power mode, the information is stored in up to M number of ways of the cache memory, where M is an integer number and 0

公开(公告)号：GB2321546B

公开(公告)日：2001-03-28

申请号：GB9724439

申请日：1997-11-20

Applicant: IBM

Inventor： KAHLE JAMES ALLAN ,  MALLICK SOUMMYA ,  MCDONALD ROBERT G ,  SWARTHOUT EDWARD L

IPC: G06F9/38 ,  G06F9/45 ,  G06F9/46 ,  G06F9/48

公开(公告)号：SG64432A1

公开(公告)日：1999-04-27

申请号：SG1997002900

申请日：1997-08-11

Applicant: IBM

Inventor： LOPER ALBERT J ,  MALLICK SOUMMYA

IPC: G06F1/26 ,  G06F1/04 ,  G06F1/32 ,  G06F9/30 ,  G06F9/38 ,  G06F15/78

公开(公告)号：SG53037A1

公开(公告)日：1998-09-28

申请号：SG1997002902

申请日：1997-08-11

Applicant: IBM

Inventor： LOPER ALBERT J ,  MALLICK SOUMMYA

IPC: G06F1/04 ,  G06F1/32 ,  G06F9/30 ,  G06F9/38 ,  G06F9/46 ,  G06F9/48 ,  G06F12/08 ,  G06F12/310

Abstract: While dispatch circuitry operates in a first power mode, per cycle of the dispatch circuitry, up to N number of instructions are dispatched to execution circuitry for execution, where N is an integer number and N>1. While the dispatch circuitry operates in a second power mode, per cycle of the dispatch circuitry, up to M number of instructions are dispatched to the execution circuitry for execution, where M is an integer number and 0

公开(公告)号：GB2321546A

公开(公告)日：1998-07-29

申请号：GB9724439

申请日：1997-11-20

Applicant: IBM

Inventor： KAHLE JAMES ALLAN ,  MALLICK SOUMMYA ,  MCDONALD ROBERT G ,  SWARTHOUT EDWARD L

IPC: G06F9/38 ,  G06F9/45 ,  G06F9/46 ,  G06F9/48

Abstract: In constructing a multiscalar program from a plurality of instructions of a selected instruction set architecture, each of a plurality of instructions are assigned to at least one of a plurality of threads 18 that each have a single entry point and multiple possible exit points. Thread code descriptive of the plurality of threads is then constructed. The thread code includes a plurality of data structures 32 that are each associated with a respective one of the plurality of threads. Each of said plurality of data structures specifies a next data structure to be processed in response to selection of one of the multiple possible exit points.

公开(公告)号：GB2321544A

公开(公告)日：1998-07-29

申请号：GB9724351

申请日：1997-11-19

Applicant: IBM

Inventor： KAHLE JAMES ALLAN ,  MALLICK SOUMMYA ,  MCDONALD ROBERT G

IPC: G06F9/38 ,  G06F9/46 ,  G06F9/48

Abstract: A processor and method of concurrently executing multiple threads are provided. The processor includes at least one register and an associated memory. According to the method, an execution control facility having first and second states is set to the first state. Execution of first and second threads is initiated such that the first and second threads are executed concurrently. Within the first thread, a first instruction is executed that stores to the associated memory a value that is referenced by a second instruction within the second thread. Thereafter, the execution control facility is set to the second state. Execution of the second instruction is permitted in response to the execution control facility being set to the second state. In another embodiment, the execution control facility is utilized to synchronize execution of multiple instructions within a second thread with execution of an instruction within a first thread.

公开(公告)号：GB2320775A

公开(公告)日：1998-07-01

申请号：GB9721623

申请日：1997-10-14

Applicant: IBM ,  MOTOROLA INC

Inventor： AFSAR MUHAMMAD NURAL ,  JESSANI ROMESH MANGHO ,  MALLICK SOUMMYA ,  MCDONALD ROBERT GREG ,  SHARMA MUKESH

IPC: G06F9/38

Abstract: To implement an early data dependency resolution mechanism for a high-performance data processing system that utilises out-of-order instruction issue, an instruction cache and a register-dependency cache are provided. The instruction cache has multiple cache lines each capable of storing multiple instructions 50. The register-dependency cache contains an identical number of cache lines each capable of storing an identical number of register-dependency units 52 as there are instructions in each of the cache lines within the instruction cache. In a single processor cycle, a group of register-dependency units 52 are fetched from the register-dependency cache. All register-dependency units that have no forward data dependency within the group of register-dependency units are identified and translated to its respective instruction utilising a corresponding cache line within the instruction cache. All of the translated instructions are issued within a next processor cycle. Since each register-dependency unit 52 has fewer bits than an instruction 50, more of them can be fetched per processor cycle.