公开(公告)号：CA1216949A

公开(公告)日：1987-01-20

申请号：CA464459

申请日：1984-10-01

Applicant: IBM

Inventor： DEAN MARK E ,  MOELLER DENNIS L

IPC: G06F9/46 ,  G06F9/38 ,  G06F11/00 ,  G06F11/07 ,  G06F13/36 ,  G06F15/16 ,  G06F15/177

Abstract: DATA PROCESSING SYSTEM INCLUDING A MAIN PROCESSOR AND A CO-PROCESSOR AND CO-PROCESSOR ERROR HANDLING LOGIC In a data processing system including a main processor and a co-processor, a logic circuit is coupled to receive error and busy outputs of the co-processor to generate an interrupt output on co-incidence of active error and busy signals and to latch the busy signal to the main processor to ensure that the main processor will honor the interrupt before executing another co-processor instruction.

公开(公告)号：BR9201974A

公开(公告)日：1993-01-12

申请号：BR9201974

申请日：1992-05-26

Applicant: IBM

Inventor： FUOCO DANIEL P ,  HERNANDEZ LUIS A ,  MATHISEN ERIC ,  MOELLER DENNIS L ,  RAYMOND JONATHAN H ,  TASHAKORI ESMAEIL

IPC: G06F13/18 ,  G06F13/36 ,  G06F13/362 ,  G06F13/14

Abstract: This invention relates to personal computers, and more particularly to personal computers in which arbitration for control over a data handling bus occurs among a plurality of "master" devices coupled directly to the bus and memory address signals are varied in response to such arbitration. The personal computer system has a high speed local processor data bus, an input/output data bus, a microprocessor coupled directly to the local processor bus, volatile memory coupled to the local processor bus for volatile storage of data, and a bus interface controller coupled directly to the local processor bus and directly to the input/output data bus for providing communications between the buses. The bus interface controller provides for arbitration among devices directly coupled to the input/output data bus for access to the input/output data bus and to the local processor bus, and for arbitration among the input/output data bus and said microprocessor for access to the local processor bus. The bus interface controller is also coupled to the volatile memory for supplying row address select signals to the volatile memory and thereby selecting data storage areas to be accessed, and responds to a change in access granted to the local bus by changing the row address select signal supplied to the volatile memory in preparation for access to potentially different data storage areas of the volatile memory.

公开(公告)号：CA2067602A1

公开(公告)日：1992-11-29

申请号：CA2067602

申请日：1992-04-29

Applicant: IBM

Inventor： FUOCO DANIEL P ,  HERNANDEZ LUIS A ,  MATHISEN ERIC ,  MOELLER DENNIS L ,  RAYMOND JONATHAN H ,  TASHAKORI ESMAEIL

IPC: G06F13/18 ,  G06F13/36 ,  G06F13/362 ,  G06F13/20

Abstract: This invention relates to personal computers, and more particularly to personal computers in which arbitration for control over a data handling bus occurs among a plurality of "master" devices coupled directly to the bus and memory address signals are varied in response to such arbitration. The personal computer system has a high speed local processor data bus, an input/output data bus, a microprocessor coupled directly to the local processor bus, volatile memory coupled to the local processor bus for volatile storage of data, and a bus interface controller coupled directly to the local processor bus and directly to the input/output data bus for providing communications between the buses. The bus interface controller provides for arbitration among devices directly coupled to the input/output data bus for access to the input/output data bus and to the local processor bus, and for arbitration among the input/output data bus and said microprocessor for access to the local processor bus. The bus interface controller is also coupled to the volatile memory for supplying row address select signals to the volatile memory and thereby selecting data storage areas to be accessed, and responds to a change in access granted to the local bus by changing the row address select signal supplied to the volatile memory in preparation for access to potentially different data storage areas of the volatile memory.

公开(公告)号：UY23414A1

公开(公告)日：1992-05-27

申请号：UY23414

申请日：1992-05-19

Applicant: IBM

Inventor： FUOCO DANEL P ,  HERNANDEZ LUIS A ,  MOELLER DENNIS L ,  ARAYMOND JONATHAN H ,  TASHAKORI ESMAEIL ,  MATHISEN ERIC

IPC: G06F1/24 ,  G06F9/00 ,  G06F13/00

Abstract: El presente invento se refiere a computadoras personales en las que se proporciona la capacidad para continuar el procesamiento a través de una señal de RESET evitando al mismo tiempo fallas del sistema. El sistema de computadora personal tiene un bus de procesador de datos de alta velocidad; un bus de datos de entrada/salida; un microprocesador reseteable acoplado directamente al bus de procesador local; y un controlador de interfase de bus acoplado directamente al bus de procesador local y directamente al bus de datos de entrada/salida para proporcionar comunicaciones entre el bus de procesador loca y el bus de datos de entrada/salida. El controlador de interfase de bus proporciona arbitraje entre dispositivos acoplados directamente al bus de datos de entrada/salida para acceso al bus de datos de entrada/salida y al bus de procesador local y arbitraje entre el bus de datos de entrada /salida y el microprocesador para acceso al bus de procesador local. El controlador de interfase de bus además reconoce el recibo de una señal de reset destinada a iniciar un reset de microprocesador y difiere la emisión de una señal de reset al microprocesador hasta que el control de interfase de bus haya bloqueado el acceso al bus de procesador local y el bus de entrada/salida por cualquiera de los dispositivos que potencialmente puedan solicitar tal acceso.

公开(公告)号：BR9005533A

公开(公告)日：1991-09-17

申请号：BR9005533

申请日：1990-10-31

Applicant: IBM

Inventor： LYFORD AVERY M ,  MOELLER DENNIS L ,  KLIM PETER J

IPC: G06F9/48 ,  G06F13/24 ,  G06F13/26 ,  G06F9/46

Abstract: A programmable interrupt controller (8) having a plurality of interrupt request inquest inputs (42, 56)and an interrupt request output (58) for connection to a central processing unit (4) (CPU) includes means for interrupting the CPU (4) over the interrupt request output (58) responsive to an interrupt request from any one of the interrupt request inputs (42, 56) and a priority resolver (92) for assigning a priority position to each of the interrupt request inputs (42, 56) to create an interrupt priority hierarchy. The interrupt controller (8) is programmable such that each interrupt request input may be independently established as responsive to either edge-triggered or level-triggered interrupt requests on a per interrupt basis. An initialization command word register (94) of the interrupt controller has a bit corresponding to each of the interrupt request inputs. Programming each of the bits of the register (94) to one of two states determines whether corresponding interrupt request inputs are edge-sensitive or level-sensitive.

公开(公告)号：CA1221173A

公开(公告)日：1987-04-28

申请号：CA473966

申请日：1985-02-08

Applicant: IBM

Inventor： DEAN MARK E ,  MOELLER DENNIS L

IPC: G06F13/28

Abstract: MICROCOMPUTER SYSTEM WITH BUS CONTROL MEANS FOR PERIPHERAL PROCESSING DEVICES A microcomputer system includes a main processor, a memory and a direct memory access controller (DMA) effective to control direct data transfer between the memory and input/output devices on channels. Bus control for data transfer is switchable between the DMA and processor by a hold request/acknowledge handshaking sequence between the DMA and processor. A control line from the channels is activated by a peripheral processing device on a channel when it wishes to gain control of the busses for data transfer. Logic means coact with the handshaking sequence to determine which device gains control of the busses. This logic is responsive to the DMA address enable output (AEN), the hold acknowledge output of the main processor (HLDA) and the channel control line output (-MASTER). When all these are deactivated, control passes to the main processor, when AEN and HLDA only are activated, control passes to the DMA controller and, when all three are activated, control passes to the peripheral processing device.