公开(公告)号：CA1320590C

公开(公告)日：1993-07-20

申请号：CA607308

申请日：1989-08-02

Applicant: IBM

Inventor： CALVIGNAC JEAN ,  LIPS JEAN-PIERRE ,  MILLET JEAN-MARC ,  MUNIER JEAN-MARIE ,  NAUDIN BERNARD

IPC: G06F15/16 ,  G06F13/38 ,  G06F13/42 ,  G06F15/167 ,  G06F15/177

Abstract: MECHANISM FOR TRANSFERRING MESSAGES BETWEEN SOURCE AND DESTINATION USERS THROUGH A SHAPED MEMORY The present invention relates to a mechanism for managing a memory shared between a number of users, so that the users may exchange messages through the memory, in a performant way. The memory comprises a linear space and a buffered space, each page of the buffered space is divided in a number m+1 of buffers of equal capacity, with m buffers devoted to the storage of data and one control buffer divided into m control blocks. There is a fixed relationship between one buffer control block and one data buffer. The control blocks are devoted to the storage of buffer and message chaining information. The linear space comprises queue control blocks, with one queue control block per user. Messages are received by a memory interface from source users and then are enqueued in link inbound queues which are dynamically built by taking buffers from the buffered space, chaining the buffers by writing buffer and message chaining information in the corresponding buffer control blocks and writing the queue head and queue tail addresses in the user queue control block. A centralized control means is designed to process, enqueue, dequeue and release orders upon requests from a user selected by an arbitrating means. When a link inbound queue becomes not empty, the memory interface sends a dequeue order request to the centralized control means, said request identifying the corresponding user FR9-88-009 queue control block. The message address is provided in response thereto with the identification of the queue control block of the destination user. Then, the memory interface sends an enqueue request to the centralized control means, said request identifying the address of the message to be enqueued and the queue control block of the destination user. The processing of this enqueue request by the centralized control means causes the messages to be enqueued in an outbound queue from which it is transferred to the destination user, by the memory interface. FR9-88-009

公开(公告)号：CA1313412C

公开(公告)日：1993-02-02

申请号：CA597345

申请日：1989-04-20

Applicant: IBM

Inventor： CALVIGNAC JEAN ,  FERAUD JACQUES ,  NAUDIN BERNARD ,  PIN CLAUDE ,  SAINT-GEORGES ERIC

IPC: H04L29/02 ,  H04L29/06 ,  H04L29/08 ,  H04L12/00 ,  G06F15/80

Abstract: FR 9 88 005 PARALLEL PROCESSING METHOD AND DEVICE FOR RECEIVING AND TRANSMITTING HDLC SDLC BIT STREAMS This invention relates to a parallel processing method and device for receiving and transmitting HDLC (high level data link control) frames, which improves the performance of a data communication apparatus in a significant way. The bit streams transporting the frames, received from lines 6 are inputted in to register 12, in such a way that n bits are processed during a time interval T. Parallel processor 10 counts the consecutive bits at 1 from the n bits received in interval T and from the bits received in the previous interval T-1, to determine when this number is found equal to 5 which bits have to be deleted, and when this number is found equal to 6 whether a flag is received. As a result it rassembles N-bits characters, with N>n, in register 16. The frame characters to be sent on lines 6 are stored into register 28, and processed in parallel in a time interval T by processor 10 which inserts 0 after five consecutive 1 as a function of the value of the N-bits and as a function of the bit of the previous character, to store into register 32, the bits which are sent on lines 6. (Figure 2)