公开(公告)号：CA2708781C

公开(公告)日：2014-07-29

申请号：CA2708781

申请日：2009-04-23

Applicant: IBM

Inventor： ARMSTRONG WILLIAM ,  GRAHAM CHARLES ,  KAO SANDY ,  LUCKE KYLE ,  NAYAR NARESH ,  OSTROWSKI MICHAL ,  RECIO RENATO ,  SWANBERG RANDAL

IPC: G06F9/455

Abstract: Multiple logical partitions are provided access to a self-virtualizing input/output device of a data processing system via multiple dedicated partition adjunct instances. Access is established by: interfacing each logical partition to one or more associated partition adjunct instances, each partition adjunct instance coupling its associated logical partition to one of a virtual function or a queue pair of the self-virtualizing input/output device, and each partition adjunct instance being a separate dispatchable state and being created employing virtual address space donated from the respective logical partition or a hypervisor of the data processing system, and each partition adjunct instance including a device driver for the virtual function or queue pair of the self-virtualizing input/output device; and providing each logical partition with at least one virtual input/output which is interfaced through the logical partition's respective partition adjunct instance(s) to a virtual function or queue pair of the self-virtualizing input/output device.

公开(公告)号：JP2010009567A

公开(公告)日：2010-01-14

申请号：JP2008259468

申请日：2008-10-06

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： GOODMAN BENJIMAN LEE ,  MILLER II MILTON DEVON ,  NAYAR NARESH

IPC: G06F9/50 ,  G06F9/46

CPC classification number: G06F9/5077 ,  G06F12/0646

Abstract: PROBLEM TO BE SOLVED: To merge two physical partitions in an information handling system. SOLUTION: The information handling system includes information processing nodes in respective physical partitions. A communications bus couples two information processing nodes together. Each node includes hardware resources such as CPUs, memories and I/O adapters. Prior to receiving a command to merge the physical partitions, the communication bus exhibits a disabled state such that the two information processing nodes are effectively disconnected. After receiving the command to merge the physical partitions, the system enables the communication bus to effectively hot-plug the two nodes together. A modified master hypervisor in one node stores data structures detailing the hardware resources of the two nodes. The modified master hypervisor may assign resources from one node to a logical partition in another node. COPYRIGHT: (C)2010,JPO&INPIT

Abstract translation: 要解决的问题：合并信息处理系统中的两个物理分区。 解决方案：信息处理系统包括各个物理分区中的信息处理节点。 通信总线将两个信息处理节点耦合在一起。 每个节点包括硬件资源，如CPU，存储器和I / O适配器。 在接收到合并物理分区的命令之前，通信总线呈现禁用状态，使得两个信息处理节点被有效地断开。 在接收到合并物理分区的命令之后，系统使通信总线能够有效地将两个节点热插拔在一起。 一个节点中修改的主管理程序存储详细描述两个节点的硬件资源的数据结构。 修改的主管理程序可以将资源从一个节点分配给另一个节点中的逻辑分区。 版权所有（C）2010，JPO＆INPIT

公开(公告)号：JP2009134716A

公开(公告)日：2009-06-18

申请号：JP2008290605

申请日：2008-11-13

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： BELL JR ROBERT H ,  COOK THOMAS EDWARD ,  NAYAR NARESH ,  LUIS BENNY CAPPS JR ,  SHAPIRO MICHAEL J

IPC: G06F12/08

CPC classification number: G06F12/0817 ,  Y02D10/13

Abstract: PROBLEM TO BE SOLVED: To provide a directory-based coherency method, system and program for giving a requested cache line from a plurality of candidate memory sources in a multiprocessor system based on a sensed temperature value or power consumption value at each memory source. SOLUTION: By providing a temperature or power consumption sensor in each of the memory sources (e.g., in a core, cache memory, memory controller, etc.) that share a requested cache line, a control logical unit uses a signal from the temperature or power consumption sensors to determine which memory source should give the requested cache line by giving the signal which directs to provide the cache line to a requester, only to the memory source which involves allowed power consumption. COPYRIGHT: (C)2009,JPO&INPIT

Abstract translation: 要解决的问题：提供一种基于目录的一致性方法，系统和程序，用于基于在每个存储器处的感测温度值或功耗值，在多处理器系统中从多个候选存储器源提供所请求的高速缓存行 资源。 解决方案：通过在共享所请求的高速缓存线的每个存储器源（例如，在核心，高速缓冲存储器，存储器控制器等中）提供温度或功率消耗传感器，控制逻辑单元使用来自 温度或功率消耗传感器，以确定哪个存储器源应该通过给出指示将请求者提供高速缓存行的信号提供给所请求的高速缓存行，而仅涉及涉及允许的功耗的存储器源。 版权所有（C）2009，JPO＆INPIT

公开(公告)号：JP2004326774A

公开(公告)日：2004-11-18

申请号：JP2004122264

申请日：2004-04-16

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： ARMSTRONG WILLIAM J ,  NAYAR NARESH ,  NORDSTROM GREGORY MICHAEL ,  TORZEWSKI TIMOTHY JOSEPH

IPC: G06F9/46 ,  G06F9/50 ,  G06F12/00

CPC classification number: G06F9/5077 ,  G06F9/542 ,  G06F2209/543 ,  G06F2209/544

Abstract: PROBLEM TO BE SOLVED: To enable optimum processes for a compartment managing operation such as a state changing operation for a variety of situations by providing a logically compartmentalized computer, a program recording medium, and a method using a flexible and adaptable communications interface between each compartment and a compartment manager.
SOLUTION: With a request for executing the compartment managing operation, a compartment function indicating whether or not an asynchronous report should be generated or suppressed in relation to the execution of the compartment managing operation by a compartment manager is supported. As a result, the asynchronous report is selectively generated in relation to the execution of the compartment managing operation based on an instruction included in the request achieved by the compartment about such an operation.
COPYRIGHT: (C)2005,JPO&NCIPI

Abstract translation: 要解决的问题：通过提供逻辑上分隔的计算机，程序记录介质和使用灵活且可适应的通信接口的方法来实现用于各种情况下的诸如状态改变操作的舱室管理操作的最佳过程 在每个隔间和一个隔间经理之间。 解决方案：支持执行车厢管理操作的请求，指示是否应该相应地由车厢管理器执行车厢管理操作来生成或抑制异步报告的车厢功能。 结果，基于包括在由隔室实现的关于这样的操作的请求中的指令，相对于车厢管理操作的执行选择性地生成异步报告。 版权所有（C）2005，JPO＆NCIPI

公开(公告)号：JP2004326749A

公开(公告)日：2004-11-18

申请号：JP2004105481

申请日：2004-03-31

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： ARMSTRONG WILLIAM J ,  MEALEY BRUCE G ,  NAYAR NARESH ,  BARARAMU SHINHAROI

IPC: G06F9/46 ,  G06F9/00 ,  G06F9/318 ,  G06F9/38 ,  G06F9/48

CPC classification number: G06F9/4812 ,  G06F9/30189 ,  G06F9/3851 ,  G06F9/485

Abstract: PROBLEM TO BE SOLVED: To provide a device and a method for switching a multithread processor between a single thread operating mode and a simultaneous multithread operating mode.
SOLUTION: The device and the method use the multithread processor having at least one of the plurality of hardware threads which can be selectively activated and deactivated in response to a control circuit. The control circuit permits or prohibits reactivation in response to, e.g., an interrupt, thus providing a function to control a method of activating a deactivated thread after the thread has been deactivated.
COPYRIGHT: (C)2005,JPO&NCIPI

公开(公告)号：JP2004295882A

公开(公告)日：2004-10-21

申请号：JP2004073504

申请日：2004-03-15

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： ARMSTRONG WILLIAM J ,  HEYRMAN PETER JOSEPH ,  NAYAR NARESH

IPC: G06F15/16 ,  G06F9/46

CPC classification number: G06F9/52 ,  G06F9/5016 ,  G06F9/5022 ,  Y10S707/99953 ,  Y10S707/99957

Abstract: PROBLEM TO BE SOLVED: To deallocate a data structure in a multithreaded computer without semaphores or spin locks. SOLUTION: Access to the data structure is governed by a shared pointer that, when a request is received to deallocate the data structure, is initially set to a value indicating to any thread that the data structure is not available. All optional threads already holding a copy of the shared pointer and capable of accessing the data structure are monitored to determine whether any thread is executing program code that is capable of using the shared pointer to access the data structure. Once the condition is met, it is ensured that no thread can potentially access the data structure via the shared pointer, and as such, the data structure can then be deallocated. COPYRIGHT: (C)2005,JPO&NCIPI

公开(公告)号：GB2516083A

公开(公告)日：2015-01-14

申请号：GB201312417

申请日：2013-07-11

Applicant: IBM

Inventor： NORTH GERAINT ,  STARKE WILLIAM ,  GUTHRIE GUY LYNN ,  WILLIAMS PHILIP ,  SHEN HUGH ,  NAYAR NARESH

IPC: G06F12/08 ,  G06F9/455 ,  G06F11/14 ,  G06F11/20 ,  G06F12/0804 ,  G06F12/0806 ,  G06F12/0875 ,  G06F12/0891 ,  G06F12/109 ,  G06F12/12

Abstract: A system comprises a processor running a hypervisor for virtual machines (VMs), a cache, e.g. a write-back cache, and a memory storing VM images for a differential check-pointing failover technique. The cache comprises rows having a memory address, a cache line, and an image modification flag. The modification flag is set (430) when a cache line is modified (420) by a backed-up VM (425), for which an image is saved in memory, while hypervisor actions in privilege mode do not set the flag. Flagged cache lines addresses are written in a log of the memory upon eviction (440) or during periodic checkpoints. Replication of the VM image in another memory can be obtained by fetching the cache lines stored at the logged addresses. Using the modification bit flag instead of dirty bit tags ensures that modified cache lines are written to the log without being flushed at the same time.

公开(公告)号：CA2365876C

公开(公告)日：2008-03-25

申请号：CA2365876

申请日：2000-03-02

Applicant: IBM

Inventor： ARMSTRONG WILLIAM JOSEPH ,  NAYAR NARESH

IPC: G06F9/50 ,  G06F9/00 ,  G06F9/46 ,  G06F9/54 ,  G06F15/16

Abstract: An apparatus, program product and method utilize an event-driven communica- tions interface to support communications between multiple logical partitions (40, 42, and 44) in a logically-partitioned computer. The event-driven communications interface is at least partially disposed within a partition manager (46) that is accessible to each of the logical partitions (40, 42, and 44). Events are typically passed between logical partitions (40, 42, and 44) in the form of messages that are passed first from a source logical partition that initiates the event, through the partition manager (46), and then to a target logical par- tition to which the event is directed, while maintaining the independent address spaces associated with the logical partitions (40, 42, and 44).

公开(公告)号：GB2513266A

公开(公告)日：2014-10-22

申请号：GB201412799

申请日：2012-12-10

Applicant: IBM

Inventor： FRAZIER GILES ROGER ,  NAYAR NARESH ,  MEALEY BRUCE

IPC: G06F9/455

Abstract: Techniques for simulating exclusive use of a processor core amongst multiple logical partitions (LPARs) include providing hardware thread-dependent status information in response to access requests by the LPARs that is reflective of exclusive use of the processor by the LPAR accessing the hardware thread-dependent information. The information returned in response to the access requests is transformed if the requestor is a program executing at a privilege level lower than the hypervisor privilege level, so that each logical partition views the processor as though it has exclusive use of the processor. The techniques may be implemented by a logical circuit block within the processor core that transforms the hardware thread-specific information to a logical representation of the hardware thread- specific information or the transformation may be performed by program instructions of an interrupt handler that traps access to the physical register containing the information.

公开(公告)号：AU2009242182B2

公开(公告)日：2014-04-03

申请号：AU2009242182

申请日：2009-04-23

Applicant: IBM

Inventor： SWANBERG RANDAL ,  OSTROWSKI MICHAL ,  ARMSTRONG WILLIAM ,  KAO SANDY ,  RECIO RENATO ,  LUCKE KYLE ,  NAYAR NARESH ,  GRAHAM CHARLES

IPC: G06F9/455

Abstract: Multiple logical partitions are provided access to a self-virtualizing input/output device of a data processing system via multiple dedicated partition adjunct instances. Access is established by: interfacing each logical partition to one or more associated partition adjunct instances, each partition adjunct instance coupling its associated logical partition to one of a virtual function or a queue pair of the self-virtualizing input/output device, and each partition adjunct instance being a separate dispatchable state and being created employing virtual address space donated from the respective logical partition or a hypervisor of the data processing system, and each partition adjunct instance including a device driver for the virtual function or queue pair of the self-virtualizing input/output device; and providing each logical partition with at least one virtual input/output which is interfaced through the logical partition's respective partition adjunct instance(s) to a virtual function or queue pair of the self-virtualizing input/output device.